08:14 <Melkhior> _florent_: in the gist https://gist.github.com/enjoy-digital/529a4d9994f0cc95e45382e4eb253b09, there's a comment "7-series SERDES in DDR mode needs 3 pulses for 1 bitslip"

08:15 <Melkhior> bit in the code I extracted from the BIOS, it seems I only have 1 pulse for 1 bitslip on my Artix-7

08:15 <Melkhior> (from a not-so-recent version of the BIOS)

08:16 <Melkhior> I'm wondering why the discrepancy, or if I'm missing something (just the one pulse seems to work for me)

08:16 <Melkhior> TIA

10:38 <_florent_> Melkhior: The 7-Series PHY was using the internal bitslip if the ISERDESE2 previously, but it has been replaced by a bitslip module in the fabric:

10:38 <_florent_> https://github.com/enjoy-digital/litedram/blob/master/litedram/common.py#L133-L155

10:39 <_florent_> I did that because as you can see, the 7-Series bitslip has a strange behaviour and this features was not available on all FPGAs, so it's easier to just do it in the fabric

10:40 <_florent_> That's the reason the workaround is no longer present in the BIOS

10:54 <Melkhior> _florent_: thanks, so just the one is OK and my code should be fine then :-)

10:54 <Melkhior> need to initialize the SDRAM from my PROM so I can then try to start up the framebuffer, as it needs the memory to be working

13:02 <somlo> _florent_: do you mind if I just merge 1058? The nextpnr timing question for gatecat is really just an orthogonal BTW, the dual-core SMP setup should work on other boards, with other toolchains...

13:03 <_florent_> somlo: sorry I saw it but forgot to merge it. That's fine yes, you can merge it.

13:04 <somlo> ok, done -- thanks!