<benh>
jevinskie[m]: in my case it works when using a LiteX SoC with VexRisc V and fails with the standlone LiteEth in microwatt... I think I got the constraints right (and there's no violation reported) but I'm crap at understanding Vivado timing reports
<benh>
LOL
<benh>
it would help if my vhdl wrapper for the core actually wired gtx :-)
<benh>
I can't believe I didn't get any warning
<benh>
interestingly enough, we don't generate any constraint for gtx
<jevinskie[m]>
I predicted it would be something simple :p
<benh>
and you were absolutely right :-)
<benh>
So... fun fact... yeterday QMtech told me that the speed grade was -1
<benh>
but I noticed their manual says -2
<benh>
and I just noticed, all their example projects are set for -2
<benh>
I can't verify because it's a stupid QR-code only FPGA and Xilinx won't let me use the decoder...
<benh>
hrm
<benh>
they are confirming it's -1 and the manual and examples are wrong :-(
<benh>
and it seems the board V1 is also supposed to be -1
<benh>
I've added a --speed-grade argument, I'm going to make it default to -1
<benh>
ah...
<benh>
so they made 2 batches of board V1
<benh>
one was -1 and one was -2
<benh>
and board v2 is all -1
<benh>
ok all good except...
<benh>
it doesn't always start properly after configuration with xc3progs
<benh>
I have to go long press the button that we connected to CPU reset and lift it
<benh>
Melkhior: yes, the QMtech guy told me "ooops ... we'll fix the doc" :-)
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<emkat>
I have extended the simsoc with a simple wb master which writes a single word to sdram when a bit in its CSR is set. I can see the wishbone transaction in the waveform after setting the CSR from the bios using mem_write, but I cannot read the value back with mem_read. I am suspecting this is a cache issue. I tried turning off the cache by specifying an L2 cache size of 0 and using the minimal variant of the cpu to no avail. How can I
<emkat>
make sure the cache is disabled or at least invalidated when I am trying to read back the value written by my custom wishbone master?
<emkat>
Update on my memory reading issue: PEBKAC. My master peripheral did not set the write enable signal. However, I am still puzzled by the output of csr.csv. Even after setting the L2 cache size to a different value (by using --l2-size in lxsim), I still see the default size of 8192 bytes for the l2_size config constant. I tried setting the l2 size to 32Ki, but it seemed to have no effect.
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