02:06 <NotHet> Is there a good way to share a LiteEth between a softcore and other logic? I'd like to use softcore for management and send UDP out quickly from logic. I am thinking of just accessing the liteeth across the wishbone, and making sure my software isn't using it at the same time. Is this a reasonable approach?

06:41 <_florent_> NoHet: You can use the Hybrid mode of the Ethernet MAC for this

06:42 <_florent_> https://github.com/enjoy-digital/liteeth/blob/master/liteeth/mac/__init__.py#L71

06:42 <_florent_> https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py#L202-L223

06:43 <_florent_> The integration still need to be simplified but you can use the code above.

10:20 <mc680898> _floent_: No cahange in symptoms with Eitherbone when I tried with master today. Still dies if I specify a trigger. Didn't get much time on that today but I have a skeleton for efinix xyloni Dev board thrown together as that is what I had on hand. Bit space constraints though, bios won't fit...

11:18 <leons> I'm currently trying to use JTAGbone for the first time. I have an FPGA board which has both the actual FPGA (Virtex 7) and a programming CPLD on the JTAG chain. Is there anything special to watch out for?

11:19 <leons> I've added the jtagbone core into my design, but the litex_server isn't too happy about it

11:21 <leons> https://gist.github.com/lschuermann/5ab53b8bfeee61449768385bc5e6cfc2

11:29 <leons> I suppose the unexpected ID errors are from the CPLD ID which OpenOCD doesn't know (at least not with the current configuration) but it does seem to try to continue with the ID it recognizes, just to fail at "Error: auto0.tap: IR capture error; saw 0x0000 not 0x0001"

11:30 <leons> Yeah, just confirmed the IDs with Vivado, "33691093" really is the FPGA 😕

13:44 <_florent_> leons: It's possible it will work even if OpenOCD does not officially support this FPGA. I think I've been able to use JTAGBone/JTAGUart on Utlrascale(+) this way and was having the same warnings/errors

13:45 <leons> _florent_: that's a good point. I actually tried using it and ran into some other errors in `litex_client.py`, given I've never used all this I didn't really investigate further. At least I now have UARTbone somewhat working with `litex_client` so I can try JTAG again as well 🙂

14:04 <_florent_> mc6808: For the Etherbone/LiteScope issue, could you try to revert LiteEth to 2021.08 (https://github.com/enjoy-digital/liteeth/releases/tag/2021.08). I'm wondering it it could be related to the recent changes to support a wider data-path

14:04 <leons> LiteX doesn't by any chance have a hardware I2C core, or even better a core for a PCA9548A I2C switch and Si5324C clock chip lying around? 🙂

14:04 <_florent_> it should be possible to only revert LiteEth

14:06 <_florent_> mc6808: For the xyloni dev board, you can maybe try to switch to SERV CPU (--cpu-type=serv), having the BIOS XiP from SPI Flash would also avoid using BlockRams, but this hasn't been tested on Efinix yet

14:13 <_florent_> leons: This?: https://gist.github.com/enjoy-digital/39fda912c94515fe87488d56057d3f68 :)

14:13 <leons> Haha I knew it would be a good idea to ask!

14:14 <leons> Did I just not manage to find it before or is this the first time you publish this?

14:15 <_florent_> I just published it

14:15 <leons> Awesome, thank you so much

14:18 <_florent_> That's the kind of code that is a bit specific to applications but happy to share it it can be useful

14:19 <leons> Yeah, apart from the actual configuration of the clock chip it's exactly what I need. If and when I have spare time I can try to make it generic but for know it's awesome to get me off the ground

14:20 <leons> These two chips seem to be a very common configuration though. The KCU116, NetFPGA SUME and apparently also your KC705 use them

17:37 <_florent_> mc6808: The SPI Flash is now working on the T120 dev kit, so you should be able to use BIOS XiP on the xyloni dev board to save BlockRams.

17:38 <_florent_> mc6808: something similar to this: https://github.com/litex-hub/litex-boards/commit/195bf176cfa9b34057b0ace8cce8dfcdeb7a3977

17:38 <_florent_> And then look at the iCEBreaker for XiP:

17:38 <_florent_> https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/1bitsquared_icebreaker.py#L82

17:38 <_florent_> https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/1bitsquared_icebreaker.py#L113-L118

17:39 <_florent_> We'll now just have to motivate trabucayre to write Efinix support to OpenFPGALoader :) (if not already done)