_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<trabucayre> _florent_: spi is already done
<trabucayre> jtag access is TBD :)
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<_florent_> trabucayre: Thanks, I just tested it and it works perfectly
<_florent_> and created https://github.com/trabucayre/openFPGALoader/pull/127 to support the dev kit I'm using
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<trabucayre> applied now!
<trabucayre> JTAG support seems straightforward to add -> this weekend (with a bit of luck and time)
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<_florent_> trabucayre: The SPI Flash support is already great, JTAG support would allow us to completely avoid the Efinix programmer (but only do it if it's also useful for you)
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<trabucayre> it's always useful :)
<trabucayre> (and in my TODO list for a while)
<trabucayre> I will try it with xyloni. T120 dev kit is a bit too expensive for me
<_florent_> trabucayre: Sure, I use the T120 because I also want to play with the LPDDR3, Ethernet and MIPI, but I should also receive a Xyloni next week
<_florent_> trabucayre: The interfaces with the FTDI are probably very similar between the different dev kits
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<trabucayre> for T120 I don't know but xyloni: interfaceA: spi, interfaceB:jtag, interfaceC:uart, interfaceD: bank power (?)
<trabucayre> I try to integrate xyloni but have an issue with PLL (xml db are a bit different for T8)
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<Guest7894> @_florent_ thanks your fix for setting the ethmac csr map helped me. I was just building xilinx_kc705 extended with a UDPIPCore and a FreqMeter instance
<Guest7894> Now after pulling the latest litex, I get a linker error : target emulation `elf64-littleriscv' does not match `elf32-littleriscv'
<Guest7894> Google says that the problem could be with march flag being set incorrectly. After looking around soc/cores, I see that the march is set correctly to rv32im for the default vexriscv + standard
<Guest7894> targets/build/xilinx_kc705/software/libc/cross.txt .. even has the flag -march=rv32im
<Guest7894> not sure what I am missing
<Guest7894> _florent_ could this error be related to some flags gone missing in the picolibc update?
<Guest7894> I can confirm that with a fresh install of litex, this still happens. I wondered if it has something to do with my RISCV install, but I just followed the steps here: https://github.com/litex-hub/linux-on-litex-vexriscv#installing-a-risc-v-toolchain
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<somlo> _florent_: commit 2c98ad94 ("fhdl/verilog: Create_print_operator/_print_slice, move code...") broke my litex/rocket build (at least) on nexys4ddr: https://pastebin.com/6DXCUBFG
<tpb> Title: ****** Vivado v2018.2 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 M - Pastebin.com (at pastebin.com)
<somlo> _florent_: my command line is "litex-boards/litex_boards/targets/digilent_nexys4ddr.py --build --cpu-type rocket --cpu-variant linux4 --sys-clk-freq 50e6 --with-ethernet --with-sdcard"
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<_florent_> somlo: Thanks, sorry for this, I'm going to look at it
<somlo> _florent_: thanks, it looks like it's building OK now
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<Guest7894> Hi All, what is the current recommended way to install riscv toolchain for vexriscv+standard ?
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