02:34 <NotHet> So couple days ago I posted that Zephyr was hanging. I think I found out why. The register definitions in the Zephyr/litex_timer.c are all wrong. If I hack it to have updated addresses Zephr runs

02:35 <NotHet> It seems like the spacing between CSRs AND the location of some of the registers changed, but I am not sure

02:35 <NotHet> Might all of the litex drivers have this? I'm going to try and figure out what all could have been impacted, but I am _totally_ new to this ecosystem and its a bit of a stumble around. What all should I be looking for?

03:03 <Wolf0> _florent_: I found this out, that's right. It's eye detection

03:20 <NotHet> Looks like the eth_liteeth.c has bad register definitions too. Bit these are a bit less straight forward to hack-to-fix

03:34 <NotHet> I created a GH issue https://github.com/zephyrproject-rtos/zephyr/issues/39298

06:53 <_florent_> NotHet : This is probably related to the merge https://github.com/enjoy-digital/liteeth/pull/74 (that removes an error CSR), I'll look at this tomorrow

10:07 <Wolf0> https://www.reddit.com/r/FPGA/comments/q515qd/things_xilinx_wont_tell_you_about_their_internal/ - It took me way too long to write this, but it came out okay

18:26 <NotHet> _florent_ thanks. I've also created a Zephyr PR for the timer fix https://github.com/zephyrproject-rtos/zephyr/pull/39304

19:26 <_florent_> NotHet: Thanks, I have a preference to revert the LiteEth change because otherwise we'll also have to update other drivers

20:58 <nosky> hi everyone, does anyone know what is the cheapest ice40 fpga that can do SATA I ?

21:02 <tnt> None of them.

21:06 <nosky> I'd have to use a SATA controller? Or maybe a fast serializer (mux) ?

21:10 <tnt> There used to be external chips but I don't think you'll find any anymore.

21:10 <tnt> But the ice40 is kind of ill suited for that anyway ... why do you want to use it to do _sata_ ?

21:11 <nosky> to get access to multi-terabyte hard drives

21:13 <tnt> If you're really intended to do that, you migh twant to get something like : https://www.redcorp.com/en/product/i-o-controller-sata-esata/startech-com/ide-pata-to-sata-adapter-converter-for-hdd-ssd-odd-40-pin-ide2sat2/75645997

21:13 <tpb> Title: STARTECH.COM Ide Pata To SATA Adapter Converter For HDD/SSD/odd 40-pin - IDE2SAT2 - Redcorp.com/en (at www.redcorp.com)

21:13 <tnt> and then just access it as PATA.

21:13 <tnt> which would be way more doable on an ice40 class device. Something like an HX8k would probably do.

21:18 <nosky> do you know what kind of chip are they using on that adapter? I want the sata connector to be on the same board as the fpga

21:21 <nosky> found it, JM20330, but it's not on sale anymore

21:23 <nosky> nevermind, found it on aliexpress. Thanks for the great idea! https://www.aliexpress.com/item/1005002000538254.html

21:23 <tpb> Title: MeiMxy JM20330 JMH330 QFP NEW HDD CHIP 1PCS|Integrated Circuits| - AliExpress (at www.aliexpress.com)

21:34 <NotHet> _florent_ Did the liteeth's change effect Timer's CSRs too? Looking to know if I should keep my PR or cancel it. Not sure how it all fits together, so maybe silly question.

22:34 <NotHet> Seems like the ethlite and the timer are unrelated problems? Like Timer CSRs are using the old style 8 bit CSR bus to access the 32 bit registers. But the LiteX SOC is using 32 bit wide CSR bus now. Which would mean keep the PR open?

22:51 <NotHet> Actually I think I see a problem in my PR now. The write into TIMER_RELOAD and TIMER_LOAD are using the 8 bit CSR bus....