_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<cr1901> Does anyone have a "known good" example of an icebreaker SoC made with litex?
<cr1901> I can't seem to get the software/bios part of mine to work ._.
<_florent_> cr1901: I'm regularly using this: python3 -m litex_boards.targets.1bitsquared_icebreaker --cpu-type=serv --build --flash
<cr1901> I'll try those later, thanks
<_florent_> DerekKozel[m]: The checkout in litex_setup is fixed with https://github.com/enjoy-digital/litex/commit/f92a185109f1bb9d9ae52cc2b588628818d249af
<_florent_> DerekKozel[m]: And Meson install/version is now checked with https://github.com/enjoy-digital/litex/commit/2a109c3a3ee1d765f6c8da7f637d76f2f10e9af7
<_florent_> This would be good to have this directly checked in picolibc but for now this will reduce the support in LiteX for this specific point :)
<DerekKozel[m]> Thanks!
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<mntmn> interesting, with quadcore vexriscv, /sbin/init hangs
<DerekKozel[m]> _florent_: Should CSR_ICAP_SEND_ADDR be CSR_ICAP_WRITE_ADDR?
<DerekKozel[m]> /home/dkozel/src/litex/build/sqrl_acorn/driver/kernel/main.c:725:40: error: ‘CSR_ICAP_SEND_ADDR’ undeclared (first use in this function); did you mean ‘CSR_ICAP_READ_ADDR’?
<DerekKozel[m]> 725 | litepcie_writel(chan->litepcie_dev, CSR_ICAP_SEND_ADDR, 1);
<DerekKozel[m]> Searching through history I can't find SEND_ADDR elsewhere
<_florent_> DerekKozel[m]: I indeed added READ capability to ICAP recently and then renamed the send CSR to write.
<_florent_> DerekKozel[m]: I just updated LitePCIe with https://github.com/enjoy-digital/litepcie/commit/2d6830fff324aa6a03c94c2258f2f15268038082, thanks for the feedback (it seems there are still things missing in the CI :))
<DerekKozel[m]> Thanks!
<DerekKozel[m]> Happy to be a manual CI here
<DerekKozel[m]> The GNU Radio -> PCIe Loopback -> GNU Radio setup is working well for data transfer now. I'm working on automating the build and load of the FPGA now
<DerekKozel[m]> Do you have any handy examples of code using the ICAP read/write?
<DerekKozel[m]> Currently I'm using the OpenOCD functions
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<mntmn> what's the right way to define pads as GPIOs that can be toggled from linux (userspace)?
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<mntmn> _florent_: i need some GPIO outputs. is there any magic i have to do to get them to show up in the dts other than name the submodule "leds"?
<mntmn> so far i did:
<mntmn> self.submodules.leds = GPIOOut(platform.request_all("gpio"))
<mntmn> self.add_csr("leds")
<mntmn> ah, i see they actually show up in the DTS now, just with status = "disabled";
<mntmn> got it to work though
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<Guest78> ilia__s .. Thanks, I did try that, and had the same ld, problem :-/
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<ilia__s> here is the env I use which includes litex and riscv toolchain and targets vexriscv: https://github.com/sergachev/litex-template
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