_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<mc6808> Another question: has anyone looked at integrating the Efinix FPGA toolchain? We are going to evaluate their devices and would like to do this with Litex
<_florent_> mc6808: I think I also got the issue when doing something similar on the Butterstick last week (also over 1Gbps Ethernet link)
<_florent_> mc6808: This could be related to https://github.com/enjoy-digital/litex/issues/1003 that increases resource usage and could degrade timings
<_florent_> I'm going to look at this
<_florent_> mc6808: Otherwise for Efinix FPGA, _franck_ has been doing some evaluations recently for a client, it's still not merge in LiteX but I'm planning to merge it soon
<_florent_> It's available here: https://github.com/fjullien/litex/tree/efinix
<_florent_> Their approach is a bit different than other vendors and all primitives are considered external to the design (similar to ASIC with the digital core + an IO pad ring), so this complicate a bit the integration in LiteX
<_florent_> but _franck_ has been able to get some simple first SoCs working with CPU/RAM/ROM/1Ggps Ethernet
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<_florent_> mc6808: I just merged the Efinix support (because it also need modifications to Migen's Memory so merging it now will avoid conflicts for #1003)
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<tnt> _franck_: oh ok, I thought it was a file entirely generated by xilinx tools but looks like it's (at least partially) manually customized. I'll leave it as is then :)
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<mntmn> hmm i'm trying to add "i2c" in my soc_capabilities in make.py of linux-on-litex-vexriscv. but it fails with: litex.build.generic_platform.ConstraintError: Resource not found: i2c:0
<mntmn> my goal is to use i2c tools from the linux userland
<mntmn> "i2c", 0 is defined in the _io array in the platform .py
<mntmn> oh i put in some print statements and i see that i2c is already taken by something else
<mntmn> ah it was already set up in the target .py, that's why!
<_florent_> mntmn: indeed, I already added it in the target
<_florent_> mntmn: if you want to check it, you can use i2c_scan command from the BIOS
<mntmn> for some reason i2c commands are not in the bios generated via linux-on-litex-vexriscv, i guess i need to enable that somewhere
<_florent_> the I2C submodule has to be named "i2c" to be enabled in the BIOS, with "i2c0" as used in linux-on-litex-vexriscv, it will indeed not be enabled
<_florent_> we should improve this
<mntmn> _florent_: ok, got it. one more thing: where is the best place to increase linux,initrd-end ?
<mntmn> i have noticed that a bit bigger cpio files fail to load
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<mntmn> _florent_: aha, thank you!
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<mntmn> hmmm, trying to understand why loading the .cpio over network would fail if it's bigger than ~24MB
<mntmn> it does not appear to be the linux,initrd-end setting in dts...
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<mntmn> ah, it's because of 512 byte tftp block size :/
<_florent_> mntmn: interesting, for now you can probably split it on your tftp server and add multiple entry in the boot.json
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<mc6808> _florent_: thanks for the efinix pointers and merging this overnight (for me)
<mc6808> _florent_: also thanks for the pointer to the fifo regression that may be the etherbone issue and merge of the fixes from #1003. I tried uartbone yesterday and go the same symptoms which had me stumped. I'm updading to master now and will report back