_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<leons> florent: it was a lot of work but I've finally got the Packetizer/Depacketizer fuzzed with a decent test suite and all known edge cases properly handled and fixed
<leons> However I'm still not sure about how they should behave if there is no last_be signal.
<leons> Currently, the Packetizer will simply throw away leftovers of a data word once last is asserted and no last_be signal is present. Is that expected?
<leons> I would have expected it to output the entire rest of the data, plus some trailing garbage (which is fine if the protocol which the Packetizer/Depacketizer is used for has its own internal length checks, etc.)
<leons> So if no last_be signal is present, I would have expected it to behave just as if last_be had the highest bit set
<leons> What do you think?
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<_florent_> G33KatWork: good you found what you were looking for. There is still not that much documentation but you can generally indeed find more complex examples while looking at the different cores/projects.
<_florent_> G33KatWork: I'm trying to list different design using Migen/LiteX here to also users to find inspiration when things are not documented: https://github.com/enjoy-digital/litex/wiki/Projects
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<_florent_> leons: Great, thanks for looking at this. Sorry I will probably need to review carefully the code to answer the questions since I wrote it a few years ago don't remember details
<_florent_> leons: If you can update the PR with the additional tests, I'll review it very soon
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<leons> florent: done. If there's any questions, for instance why I've done something in a particular way, please don't hesitate to ask
<leons> Sorry it took this long, there once again were edge cases I've discovered
<leons> But now, finally, all defined tests pass
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