_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<sajattack[m]> <Melkhior> "sajattack: the L2 matters..." <- thanks for the tip, got my 8 fpus running now 😄 https://hastebin.com/aqafuhenux.apache
<tpb> Title: hastebin (at hastebin.com)
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<sajattack[m]> anyone know what to do about this buildroot error? https://hastebin.com/oyocegavok.rb
<tpb> Title: hastebin (at hastebin.com)
<trabucayre> sajattack[m]: it's a mismatch between linux header (Toolchain -> Custom kernel headers series) and your kernel
<sajattack[m]> yeah I got it sorted I think by forcing it to 5.12 in buildroot
<sajattack[m]> even though I'm running 5.14
<trabucayre> need to select BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_12 for Toolchain -> Custom kernel headers
<sajattack[m]> so not sure
<trabucayre> grep PATCHLEVEL output/build/linux-something/Makefile
<trabucayre> and
<trabucayre> grep PATCHLEVEL output/build/linux-header*/Makefile
<trabucayre> and if you modify linux header version you must run `make clean` before `make`
<sajattack[m]> yeah that's what I did I think
<sajattack[m]> but I used the menuconfig
<sajattack[m]> * running 5.14 on my host
<trabucayre> not your host :)
<sajattack[m]> ok
<trabucayre> linux version must be the same for linux-header (toolchain) and kernel for your target
<sajattack[m]> ah ok
<sajattack[m]> so why wasn't it to start with?
<sajattack[m]> it was set to like "match whatever"
<sajattack[m]> and I just overrode it to 5.12
<trabucayre> when linux header is not explictly selected default one is used
<sajattack[m]> is it because of the buildroot version I downloaded?
<sajattack[m]> now I'm uploading a 12MB rootfs at 8KB/s
<trabucayre> for current master branch it's 5.13
<sajattack[m]> <_florent_> "BTW once you have something..." <- https://github.com/litex-hub/linux-on-litex-vexriscv/issues/249
<tpb> Title: Config.in.host « linux-headers « package - buildroot - Buildroot: Making Embedded Linux easy (at git.buildroot.net)
<sajattack[m]> yeah it was set to "same as kernel being built"
<sajattack[m]> and I was building 5.12
<sajattack[m]> so I don't really understand why it had to change to 5.12
<sajattack[m]> but whatever
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<sajattack[m]> <Melkhior> "depends on your use case I guess..." <- did you recompile on-device? I'm trying to figure out how to get a compiler into the buildroot, seems buildroot doesn't let you do that because they want to save space?
<sajattack[m]> all it'll give me is binutils
<sajattack[m]> I guess I could do a filesystem overlay
<sajattack[m]> but then I'd need a way to cross-compile gcc which doesn't sound like a good time
<sajattack[m]> I've done it before raspberry pi actually
<sajattack[m]> but it wasn't especially fun
<sajattack[m]> I think I just delayed my "what the hell do I do with this now" by a few days 😆
<sajattack[m]> but no regrets
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<cr1901> >(3:30:28 AM) sajattack[m]: but then I'd need a way to cross-compile gcc which doesn't sound like a good time
<cr1901> I wish the targets "all-{,target}-*" were documented instead of me having to read the source of the gcc Makefile (which is maybe the only use I've seen of GNU autogen in the wild)
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<_florent_> sajattack[m]: Thanks for the issue, I'll try to simplify using this configuration.
<_florent_> That's also a bit sad to see 8KB/s upload on a PCIe link is usually use on other designs for >12Gbps DMA xfers :) I'll have a closer look at litex_server/litex_term use over PCIe to see where we loose that much efficiency...
<_florent_> tpw_rules: Thanks for the files, I just had a look at it: They are very similar to the one I'm generating locally and ./sqrl_acorn.py --with-pcie --uart-name=crossover --build also fails here.
<_florent_> I'll improve the constraints, for now you can comment these lines: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/sqrl_acorn.py#L107-L111
<_florent_> tpw_rules: sajattack[m] is using a very similar configuration I think
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<sajattack[m]> _florent_: would I see any benefits updating to that or do the timing constraints not effect much?
<_florent_> not really but the P&R will be faster
<sajattack[m]> oh ok
<sajattack[m]> yeah I didn't expect it would change much
<sajattack[m]> faster pnr is good though
<sajattack[m]> seeing as I'm building hexacore hexafpu
<sajattack[m]> looking for things to do and having trouble sleeping last night, I got a rust binary compiled for vexriscv linux using the rust std library
<sajattack[m]> I'm about to see if it works once the cpio uploads
<sajattack[m]> 96%
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<tpb> Title: hastebin (at hastebin.com)
<sajattack[m]> 🥳
<_florent_> sajattack[m]: nice
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<sajattack[m]> I built this for 32 bit and used it as the linker for the rust target riscv32gc-unknown-linux-gnu with -Zbuild-std https://github.com/riscv-software-src/riscv-gnu-toolchain
<tpw_rules> i more mean the gateware and loading linux onto it
<sajattack[m]> https://gist.github.com/sajattack/701a8d677ec01fe51b423ebbfa013c22 oh ok, I thought you meant the rust
<sajattack[m]> for the bitstream, I made some notes here https://github.com/litex-hub/linux-on-litex-vexriscv/issues/249
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<jevinskie[m]> I modified serial2tcp into serial2udp so you get first/last framing. Hooked it up to SPIMaster with a simple stream FSM for a SimSPIMaster :)
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<G33KatWork> heyjo! I have a question about simulating something I am currently writing using litex - it might be more of a migen question, but anyway, here we go: I am trying to build a receiver for a protocol. To test the synchronization features of my receiver, I need a sender in a testbench in a different clock domain than the receiver. I already have two generators in my testbench, one for the transmitter which
<G33KatWork> shoves bits with the right timing over a pad into the receiver running in another generator. Now to simulate a slowly drifting clock, I want the sender and receiver generator to run in different clock domains. Let's say the receiver runs at 10MHz, I want the sender to run at a sliiiighly slower or fast clock. Is that possible? I couldn't find an example that actually does this, so I thought I'd ask here.
<G33KatWork> nevermind. I just got the idea to check out the more complicated external cores like litesata and I immediately found it. Just add clocks in the clocks dict and change the list of generators passed to run_simulation to a dict of lists where the key is the clock domain name and the value the list of generators
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