08:13 <_florent_> kbeckmann: nice, thanks for sharing the results. 1:1 will indeed provide less bandwidth but also less latency.

08:15 <_florent_> kbeckmann: if you disable the refresh temporarily, that would be good to add a mechanism to ensure that all the rows as still refreshed in the refresh time (64ms)

08:16 <_florent_> jevinskie[m]: sorry I'm not sure to understand what is failing, could you share more info or a log?

08:18 <kbeckmann> Right, 1:1 removes the need for CDC flip flops so I get better latency that way. Good point wrt the refresh. Currently I just disable the timer during an active read, and when it finishes the times is reset. So if there are lots of bus reads it's possible that the timer never expires, I should fix that.

18:15 <yosys-questions> Is there a way to access csr registers over UART? At the moment the UART serial is taken by the CPU terminal. Is there a way to detach that terminal from CPU and give it to UARTwishbonebridge?

18:17 <yosys-questions> Is that what add_uartbone does?

18:59 <jevinskie[m]> yosys-questions: use uart=“crossover” to put the uart on the uartbone bridge

19:00 <jevinskie[m]> Then you access your CSRs over uartbone and the terminal is also accessed via CSRs over the same uartbone bridge