_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<leons> Is it possible that latest LiteX master depends on a pythondata_software_picolibc which is not yet on GitHub? 🙂
<leons> For anyone else stumbling over that on IRC: https://github.com/enjoy-digital/litex/issues/1045
<_florent_> leons: it's still currently on https://github.com/antmicro/ but I'm going to put it on litex-hub
<_florent_> leons: it should be good now.
<leons> Awesome, thanks. There's still an issue with upstream picolibc which prevents compilation on my distribution but I'm going to open a PR with upstream for that
<_florent_> ok, thanks. Please share the PR in case it can be useful to others
<_florent_> It seems libliteeth compilation is also broken, I'm looking at this
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<leons> florent: submitted it upstream via mailing lists. My distro just doesn't have /bin/bash, so it's a simple patch to change it all to /usr/bin/env bash
<acathla> I'd like to have a memory mapped on the wishbone bus and available to a my module. What's the best way to do that? I tried to instantiate a SRAM module from wishbone.py and add a second port but it seems it does not like it.
<acathla> It seems to build now, that was bad copy/paste as usual...
<zyp> hmm, I'm not having luck getting picolibc to build: https://paste.jvnv.net/view/eOQwz
<tpb> Title: JVnV Pastebin – View paste – Untitled (at paste.jvnv.net)
<leons> zyp: this is on a Mac I presume? although that error doesn't sound like it should have anything to do with that
<zyp> yes
<acathla> I'm not having luck either : Expression of unrecognized type: 'ClockSignal' , I didn't touch a thing about clocks...
<somlo> managed to build a bitstream with picolibc-based bios for rocket, but not getting any terminal output (blinky lights are there, but nothing on the uart)
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<somlo> looks like the uart irq (if not irq support in general) has come "unglued"..
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<somlo> _florent_: when you read this: in simulation, I get to the prompt, but can't type anything (uart irq isn't firing); on the fpga, I get no output from the uart at all (probably getting stuck somewhere before any output is generated, likely still due to irq issues)
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<somlo> I'm going to try to track down what about the picolibc resulted in Rocket IRQs getting "disconnected" (beginning with whether this code: https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/bios/isr.c#L32 is still getting compiled in and called from the rocket trap handler)
<somlo> ok, so the code *is* being reached and compiled (added a "#error" directive to make sure, and it triggered :)
<somlo> so now I'm confused, as that hypothesis was the "low hanging fruit" :)
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