00:40 <jevinskie[m]> Hmm that had a non-climactic resolution. Setting MDIO HW_CONFIG to “GMII” mode was the trick to making everything Just Work in 100 mbps mode :))

17:23 <jevinskie[m]> Is there a way to get a port name from a ClockSignal that connects to it? I’m trying to work around altera synthesizing away “keep” annotated symbols by using get_ports in addition to get_nets in the SDC generation but I’ve not found a way to “see” that two signals are simply assigned to each other

20:11 <jevinskie[m]> It’s super ugly but I hacked something up that looks through comb statements for _Assign and _Slice of the clock port to the clock net. I doubt Xilinx stuff builds anymore now though…