08:49 <pftbest> Hello. Can somebody check if "--trace-fst" works with your verilator version? I had to change TRACE_FST to VM_TRACE_FST in litex/build/sim/core/veril.cpp to make it work for me

08:50 <pftbest> So now I'm not sure if I should make a pull request because it may be specific to my verilator version

08:50 <pftbest> I'm using "Verilator 4.202 2021-04-24 rev v4.200-110-g15f7741ea"

14:15 <_florent_> pftbest: Hello, I could do the test tomorrow, you can eventually open an issue to discuss this

14:17 <pftbest> _florent_: thanks, I will open a PR with the fix, you can then close it if it's not needed

14:17 <_florent_> tnt: For the internal signals of a Module, we don't have explicit naming convention. When it becomes a bit ambigious, I personnaly just add some # o / # i comments after the signal declaration

14:17 <_florent_> pftbest: thanks

14:36 <pftbest> _florent_: https://github.com/enjoy-digital/litex/pull/957

15:28 <tnt> Pfew, finally pushed a bunch of examples for the cores I wrapped, with appropriate firmware/drivers to actually do something.

19:19 <_florent_> tnt: nice, I'll do a test on the iCEBreaker next week. We can add a link to it in https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources or https://github.com/enjoy-digital/litex/wiki/Projects if you want

19:32 <tnt> _florent_: btw, something that came up too is the ability to add -D verilog defines when reading source files. Don't think this is currently possible.

19:33 <tnt> I'll probably work around it by rewriting source files to temporary files and adding defines manually at the top but just a feature that occured to me.