23:44 <tcal> acathla: tnt: I agree a Fomu- (or even ice40up5k-)optimized prebuilt VexRiscv would be useful --- I've been building my own, sometimes with muldiv (not single-cycle, although I can get that to fit as well with a bit of hacking). Xobs has also made a few versions: https://github.com/xobs/VexRiscv-verilog . As you were discussing, the usefulness of the I-cache depends on whether you plan to execute out of SRAM or out of SPI flash