<_florent_>
tnt: I see you have various cores at: https://github.com/no2fpga, are you only interested for LiteX wrappers/integration for the USB core or also for the other cores?
<_florent_>
to ease reuse with LiteX cores, there are different options, this could be a repository in https://github.com/no2fpga that would provide the wrappers for LiteX (and eventual examples) or we could also create a pythondata-misc-no2fpga in LiteX-Hub that would provides your cores + wrappers
<tnt>
_florent_: so the way I started this morning is creating a no2migen repo that will eventually contain both a no2migen.migen and no2migen.litex submodule (since some cores would not really be meant for litex specifically).
<tnt>
I'm finishing up a proto right now and will push it for you to have a look. I'm removing the dependency on hardcoded path and moving to pkg_resources to get the sources now.
<acathla>
tnt, the minimal vex does not have any cache, hardware mul, etc, so everything is very slow. Lite vex is too big for the fomu with USB. But by default the FOMU uses a vex with just an instruction cache. It seems to take only a few LC (only 13 ! on my last test) and some RAM.
<tnt>
Anyway, I changed my code to use minimal and execute all from SRAM (copied from flash at boot) and that works just fine. 64k/128k is plenty of space, no need to bother with flash XiP for that example.
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<acathla>
tnt, adding instruction cache to the minimal vexriscv takes only 13 LC
<acathla>
And yes, copying everything to RAM helps a lot too =)
<tnt>
acathla: ah yeah, but I don't think there is a pre-done litex variant that's just `minimal+icache`
<tnt>
makes it way less convenient for a code example.
<acathla>
we could add that variant to litex =)
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<_florent_>
tnt: no2migen looks very nice! I'll test the build in the next days and will also try to implement #951 while doing this
<tnt>
_florent_: Thanks. Still need to add examples. ATM I just have a hacked up example for the icebreaker with usb pmod. I'll probably add one for the icebreaker-bitsy / fomu.
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<_florent_>
tnt: Examples can indeed simplify reproducing things. BTW, you can create examples by copying the LiteX targets, but you can also build your design on top of the LiteX target and just integrate the additional logic, like done here for example on LiteSDCard bench that is based on Arty target and just add some additional logic to it: https://github.com/enjoy-digital/litesdcard/blob/master/bench/arty.py
<tnt>
Yeah, I was planning on copying the targets files and just stripping them :p
<_florent_>
which USB PMOD are you using? (I can try to have the hardware to be able to test things)
<tnt>
Can a core itself know what address its mapped to and generates some #defines ? The tinyusb driver needs a few specific #defines to match the core config and its place in the address space and ideally I'd like to have the core itself generate those rather than the 'target.py'.
<tnt>
_florent_: well ... huh, I just have a USB cable that I cut up and wired to a pin header with DP/DN and a 1.5k through hold resistor directly soldered to it.
<tnt>
This should also work. In the PR I opened I copied the various pinouts defined in LUNA.
<_florent_>
for now, the #defines are generated with soc.add_constant, so if you want the core to generate add constant, you have to pass soc to your Core or at least have a method doing this (with soc as argument). But we could also eventually add a mechanism to allow the SoC to collect the constants defined in submodules.
<tnt>
_florent_: And how can the core gets access to where it was mapped ?
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<tnt>
I guess I don't really need that though, as long as I have the 'name' of the region I can use offsets wrt `REGIONXXX_BASE`.
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<_florent_>
tnt: The mapping is indeed handled at the SoC level, the firmware/software can just reuse the generated mapping.
<_florent_>
In some cases, it's not convenient to let the SoC do all the mapping automatically (ex for retro-compatibility), so the user can also force it when required
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