00:58 <cr1901> tcal: In late 2018, I ported litex/micropython to TinyFPGA Bx- a 1kB icache gets you twice the performance from my testing

00:58 <cr1901> when running from SPI flash*

00:59 <cr1901> Could be faster if the core prefetches/anticipates cache lines, but I never pursued adding this to LiteX

01:58 <promach[m]> How to get around the above ISE placement error ?

01:58 <promach[m]> https://github.com/promach/DDR/blob/main/serdes_n_to_1_ddr_s8_diff.v#L97

01:58 <promach[m]> https://github.com/promach/DDR/blob/main/ddr3_memory_controller.v#L752

13:40 <promach[m]> Why phase detector requires TWO ISERDES2 primitives ?

13:40 <promach[m]> https://github.com/promach/DDR/blob/main/phase_detector.v

13:40 <promach[m]> https://www.xilinx.com/support/documentation/user_guides/ug381.pdf#page=84

19:24 <jevinskie[m]> If I’m reading the litescope driver right, it doesn’t use burst transfers when uploading the samples. Would it be as easy as batching the requests into 255 bursts to increase the upload speed?

19:39 <_florent_> jevinskie[m]: the driver does not explicitely use burst transfers, but litex_server should be able to merge read requests automatically

19:39 <_florent_> https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_server.py#L24

19:41 <_florent_> but that's True that litescope uploads will indeed not break speed records

19:41 <_florent_> If you doing it over UART, increasing the baudrate can be useful

21:31 <jevinskie[m]> Cool trick! Yeah I cranked it up to 3 mbaud but haven’t tried faster. Jtag seems to be faster for me. Luckily it should be much less of an issue when the intel cyclone 10 board with dual Ethernet arrives so I can test my Ethernet design on one and have a high speed litescope link left over :)