_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
nelgau has quit [Remote host closed the connection]
nelgau has joined #litex
cr1901 has quit [Quit: Leaving.]
cr1901 has joined #litex
Degi_ has joined #litex
Degi has quit [Ping timeout: 250 seconds]
Degi_ is now known as Degi
nelgau has quit [Remote host closed the connection]
nelgau has joined #litex
nelgau has quit [Ping timeout: 258 seconds]
tpb_ has joined #litex
tpb has quit [Killed (NickServ (GHOST command used by tpb_))]
tpb_ is now known as tpb
TMM__ has joined #litex
TMM_ has quit [*.net *.split]
nelgau has joined #litex
nelgau has quit [Ping timeout: 244 seconds]
TMM__ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
FabM has joined #litex
lexano has quit [Ping timeout: 244 seconds]
lexano has joined #litex
nthiel has joined #litex
pftbest has quit [Remote host closed the connection]
nthiel has quit [Remote host closed the connection]
C-Man has quit [Ping timeout: 250 seconds]
pftbest has joined #litex
nthiel has joined #litex
nthiel has quit [Remote host closed the connection]
nthiel has joined #litex
nthiel has quit [Remote host closed the connection]
nthiel has joined #litex
david-sawatzke[m has quit [Remote host closed the connection]
jryans has quit [Write error: Broken pipe]
shoragan[m] has quit [Write error: Connection reset by peer]
sajattack[m] has quit [Remote host closed the connection]
dcallagh has quit [Remote host closed the connection]
Leon[m] has quit [Remote host closed the connection]
jevinskie[m] has quit [Read error: Connection reset by peer]
jryans has joined #litex
shoragan[m] has joined #litex
Leon[m] has joined #litex
dcallagh has joined #litex
sajattack[m] has joined #litex
david-sawatzke[m has joined #litex
jevinskie[m] has joined #litex
<dcallagh> does anyone know how to populate initial values for LRAM in Radiant Verilog?
<dcallagh> the litex.soc.cores.ram.lattice_nx.NXLRAM class doesn't know how to do that currently, but i'm trying to add it, so that i can place BIOS in an LRAM and execute from it
<dcallagh> seems like the Verilog module for the LRAM takes a long sequence of parameters like `INITVAL_00` .. `INITVAL_7F` containing a 640-byte hex string
<dcallagh> but i can't find any docs from Lattice about the exact meaning of those parameters
<dcallagh> gatecat: it looks like you have implemented support for those parameters in yosys/prjoxide, do you know if there is any docs for them or how exactly i can use them?
<dcallagh> i'm too much of a noob to understand what the code in prjoxide is actually doing with those parameters
<tpb> <https://x0.no/4uxdq> (at github.com)
<gatecat> each 40 bits of each init string is actually used only for 32 bits with 8 bits of padding
<gatecat> I don't know why this is, but I'm sure it made sense to someone at Lattice
<dcallagh> ha. okay. so i can fill those parameters with 32 bits of real data and 8 bits of zeroes alternating?
<gatecat> yeah, that seems like what I worked out...
<dcallagh> that explains why 640*0x80 adds up to 80KB but the LRAM is only 64KB
<gatecat> right
<dcallagh> okay. tomorrow i'll try feeding that to radiant and see what happens. thanks
<dcallagh> am i right in assuming that Lattice do not document this anywhere?
<dcallagh> they expect everyone to just design their stuff in Radiant GUI with pointy-clicky and leave their Verilog modules totally undocumented?
<dcallagh> the Radiant GUI offers to fill in an initial value into LRAM for me but that obviously doesn't help Litex generating Verilog
<gatecat> yeah I don't think there are any good Lattice docs about this
nthiel_ has joined #litex
nthiel_ has quit [Remote host closed the connection]
C-Man has joined #litex
pftbest has quit [Ping timeout: 245 seconds]
FabM is now known as bisamme
bisamme is now known as FabM
pftbest has joined #litex
lexano has quit [Quit: Leaving]
lexano has joined #litex
C-Man has quit [Ping timeout: 252 seconds]
C-Man has joined #litex
_franck_1 has joined #litex
_franck_ has quit [Ping timeout: 245 seconds]
_franck_1 is now known as _franck_
nelgau has joined #litex
nelgau has quit [Ping timeout: 245 seconds]
C-Man has quit [Ping timeout: 272 seconds]
peeps[zen] has joined #litex
peepsalot has quit [*.net *.split]
FabM has quit [Remote host closed the connection]
tpb_ has joined #litex
tpb has quit [Killed (NickServ (GHOST command used by tpb_))]
tpb_ is now known as tpb
_franck_0 has joined #litex
_franck_ has quit [*.net *.split]
_franck_0 is now known as _franck_
C-Man has joined #litex
nthiel has quit [Quit: Textual IRC Client: www.textualapp.com]
lkcl_ has joined #litex
pftbest has quit [Remote host closed the connection]
Coldberg has joined #litex
pftbest has joined #litex
chipdsgr has quit [Ping timeout: 272 seconds]
C-Man has quit [Ping timeout: 265 seconds]
<zyp> _florent_, boards for the stuff I've been working on have arrived and things are starting to fall into place: https://bin.jvnv.net/file/XHzyw.jpg https://bin.jvnv.net/file/IvGDv.png :)
<zyp> for now I've copied Greg's hyperram init code and patched that into the bios, but I wonder what would be the reasonable way forward with that?
<zyp> should I just add a liblitehyperbus in the same style as the other init codes, or would you like me to make a proposal for how to hook code into the bios without being part of the litex repo itself?
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
pftbest has quit [Remote host closed the connection]
pftbest has joined #litex
pftbest has quit [Remote host closed the connection]
pftbest has joined #litex
awordnot has quit [Read error: Connection reset by peer]
awordnot has joined #litex
toshywoshy has joined #litex
pftbest has quit [Remote host closed the connection]
pftbest has joined #litex
awordnot has quit [Ping timeout: 264 seconds]
awordnot has joined #litex