05:55 <_florent_> OmkarBhilare[m]: To generate a standalone LiteDRAM core, you'll create a yaml config file and then run litedram_gen my_config.yml to generate the verilog

05:56 <_florent_> OmkarBhilare[m]: It's indeed possible to generate the core without the CPU, but in this case you'll have to do the SDRAM initialization yourself

05:57 <_florent_> For SDRAM, the initialization is very simple (just a few write to the MR registers), so it indeed wasting resources for a CPU just for this

05:57 <_florent_> It's also possible to do it with a simple FSM for SDRAM

05:58 <_florent_> The generator has only been used to generate DDR2/3/4 standalone cores for now, so SDRAM support would need to be added

05:59 <_florent_> I could eventually do it or give directions for this

06:00 <_florent_> Otherwise, to remove the CPU and expose a Wishbone interface instead, you can just set CPU to None in the .yml file, ex:

06:00 <_florent_> https://github.com/antonblanchard/microwatt/blob/master/litedram/gen-src/arty.yml#L6

06:00 <_florent_> https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py#L532

06:02 <OmkarBhilare[m]> <_florent_ "I could eventually do it or give"> Hi _florent_ thanks for the info.

14:38 <tnt> Is there some naming convention for signals meant to be connected to ? Like i_ / o_ prefix or something ?