_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> cr1901: Yes sure, we could merge a Jcore initial support. Are you planning to allow compilation with GHDL/Yosys as we are doing with Microwatt? (this would be useful for tests with litex_sim).
<Melkhior> _florent_: word-addressing didn't solve my problem :-( must be missing something.
<Melkhior> yet still only claims a 4 GiB address space in my log (INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.)
<Melkhior> mmmm I don't see that width propagated to the bus, so it might use the default 30
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<cr1901> _florent_: At present, GHDL compilation is the only thing I'm supporting
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<geertu> cr1901: Cool. Is this J2 (nommu) or J4 (mmu)?
<cr1901> geertu: J1
<cr1901> so "a stripped down J2"
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<Melkhior> _florent_: got my bug; I wasn't re-setting SEL so it reseted to 0 when I was sending data on the bus...
<Melkhior> presumably with no bytes selected it's normal for the CSR 're' signal to never be asserted, so the chaser kept chasing
<Melkhior> I can now change the LED status from the PROM through SBus & Wishbone :-)
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<david-sawatzke[m> Is there any way to "properly" do a register array in litex? Like dimElementGroup in svd?
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<mithro> Just a reminder that I have a spreadsheet at https://docs.google.com/spreadsheets/d/1XTHfdYXuvwoYdPXm4M6qDA0D2fZCPy220-9q6qZpTw4/edit#gid=566444457 with a bunch of information about LiteX boards, CPU, firmware, drivers, etc
<tpb> Title: LiteX Soft-CPU, FPGA and Firmware Support - Google Tabellen (at docs.google.com)
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