_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<jevinskie[m]> @florent thanks for the pointers! I’ve got my simulation set up with a 64 bit counter and I’m setting the valid flag every 16 cycles. I’ve got a pipeline with a 64-to-8 converter and now I’m fiddling around with Endpoint
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