04:13 <alanvgreen_> I'm using a ULX3S board, and the video frame buffer. The video signal seems to drop while doing intensive memory access. I'm guessing that's due to a buffer underrun. The SoC sys_clk_freq is limited to about 50MHz. Is there a convenient way to increase the SDRAM speed to 100MHz, while keeping sys_clk_freq at 50MHz?

07:42 <mupuf> _florent_: Nice stories on twitter :D

08:39 <alanvgreen_> Answer to me: This is exactly what the sdram_rate parameter does. Use sdram_rate="1:2" to get a double speed clock, which is exactly the 100MHz I thought I wanted. BIOS reports approximately the same read and write speeds, but HDMI signal no longer drops. Hooray!

09:35 <gatecat> alanvgreen_: the read and write speeds in the BIOS are as measured by the CPU and depend a lot on CPU performance - they're not DMA speeds or anything

09:35 <gatecat> so that they don't change isn't a problem here

09:51 <_florent_> mupuf: Thanks, I was procrastinating a bit :)

09:52 <_florent_> alanvgreen_: 1:2 SDRAM ratio will indeed provide you 2X SDRAM bandwidth, but as gatecat said, it's possible you won't see it from the BIOS Memtest since the CPU is already the bottleneck with the 1:1 ratio

09:54 <_florent_> if you call add_sdram with "with_bist=True", you'll have a sdram_bist command in the BIOS that you could use to measure the SDRAM bandwidth

09:54 <_florent_> https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1225

09:55 <_florent_> this will add a hardware generator/checker, useful to do initial tests on SDRAM, but it's using resources, so generally disabled on designs once DRAM is validated

09:56 <_florent_> Otherwise, for the VideoFramebuffer, you can also play with the fifo_depth to compensate temporary unavailability of the DRAM: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/video.py#L609

09:57 <_florent_> the default value should be a good compromise between resource usage/amount of buffering, but that's adjusting it can probably be interesting on some systems

13:20 <alanvgreen_> gatecat: Makes sense, thanks for the explanation

13:21 <alanvgreen_> _florent_: Thank you for the pointers to the bist function and fifo depth parameter!

14:33 <Melkhior> _florent_: is there some documentation explaining the sdram initialization process ?

14:34 <Melkhior> Trying to understand it, but in 'sdram_write_latency_calibration' I have test 'if (_sdram_write_leveling_bitslips[module] < 0)', and that global array is never initialized in my case (SDRAM_PHY_WRITE_LEVELING_CAPABLE is not set)

14:36 <Melkhior> So the array sould be all-O (it's a global), so the test is always false, so 'bitslip' is always set to the array content, i.e; to 0 ... making the test loop somewhat redundant

14:36 <Melkhior> Must be missing something ...

19:28 <OmkarBhilare[m]> Hello,

19:28 <OmkarBhilare[m]> I wanted to use litedram core in my Google summer of code project under beagleboard org.

19:28 <OmkarBhilare[m]> The project is BeagleWire Software. The BeagleWire is a FPGA cape for beaglebone black based on iCE40HX. The cape has 32 MB SDRAM. I wanted to produce standalone verilog code for SDRAM controller without the CPU. I have been exploring the litedram but had couple of doubts related to it.

19:29 <OmkarBhilare[m]> Can I ask my doubts here?

20:55 <jevinskie[m]> Yes please. Don’t need to ask to ask :)

21:00 <OmkarBhilare[m]> Actually my rest of the Designs were in Verilog. So I wanted to produce standalone verilog code with CPU as none.

21:00 <OmkarBhilare[m]> So wanted to ask does litedram can produce the core without the cpu, just exposing the wishbone will do.

21:00 <OmkarBhilare[m]> https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py

21:00 <OmkarBhilare[m]> For standalone I was looking into this.

21:00 <OmkarBhilare[m]> https://github.com/enjoy-digital/litedram/tree/master/examples

21:00 <OmkarBhilare[m]> I see some yaml examples here