_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
Coldberg has quit [Ping timeout: 256 seconds]
jediminer543_ has quit [Read error: Connection reset by peer]
Degi_ has joined #litex
Degi has quit [Ping timeout: 265 seconds]
Degi_ is now known as Degi
aquijoule_ has joined #litex
aquijoule__ has quit [Ping timeout: 258 seconds]
alanvgreen_ has joined #litex
<alanvgreen_> I'm using a ULX3S board, and the video frame buffer. The video signal seems to drop while doing intensive memory access. I'm guessing that's due to a buffer underrun. The SoC sys_clk_freq is limited to about 50MHz. Is there a convenient way to increase the SDRAM speed to 100MHz, while keeping sys_clk_freq at 50MHz?
Leon[m] has joined #litex
alanvgreen_ has quit [Quit: Connection closed for inactivity]
FabM has joined #litex
FabM has quit [Changing host]
FabM has joined #litex
<mupuf> _florent_: Nice stories on twitter :D
sajattack[m] has joined #litex
aquijoule_ has quit [Quit: Leaving]
aquijoule_ has joined #litex
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex
alanvgreen_ has joined #litex
vomoniyi[m] has joined #litex
<alanvgreen_> Answer to me: This is exactly what the sdram_rate parameter does. Use sdram_rate="1:2" to get a double speed clock, which is exactly the 100MHz I thought I wanted. BIOS reports approximately the same read and write speeds, but HDMI signal no longer drops. Hooray!
cr1901 has quit [Ping timeout: 240 seconds]
cr1901 has joined #litex
Coldberg has joined #litex
<gatecat> alanvgreen_: the read and write speeds in the BIOS are as measured by the CPU and depend a lot on CPU performance - they're not DMA speeds or anything
<gatecat> so that they don't change isn't a problem here
<_florent_> mupuf: Thanks, I was procrastinating a bit :)
<_florent_> alanvgreen_: 1:2 SDRAM ratio will indeed provide you 2X SDRAM bandwidth, but as gatecat said, it's possible you won't see it from the BIOS Memtest since the CPU is already the bottleneck with the 1:1 ratio
<_florent_> if you call add_sdram with "with_bist=True", you'll have a sdram_bist command in the BIOS that you could use to measure the SDRAM bandwidth
<_florent_> this will add a hardware generator/checker, useful to do initial tests on SDRAM, but it's using resources, so generally disabled on designs once DRAM is validated
<_florent_> Otherwise, for the VideoFramebuffer, you can also play with the fifo_depth to compensate temporary unavailability of the DRAM: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/video.py#L609
<_florent_> the default value should be a good compromise between resource usage/amount of buffering, but that's adjusting it can probably be interesting on some systems
promach[m] has quit [Quit: Bridge terminating on SIGTERM]
sajattack[m] has quit [Quit: Bridge terminating on SIGTERM]
Leon[m] has quit [Quit: Bridge terminating on SIGTERM]
vomoniyi[m] has quit [Quit: Bridge terminating on SIGTERM]
jryans has joined #litex
shoragan[m] has joined #litex
jevinskie[m] has joined #litex
Leon[m] has joined #litex
CarlosEDP has joined #litex
dcallagh has joined #litex
promach[m] has joined #litex
vomoniyi[m] has joined #litex
DerekKozel[m] has joined #litex
david-sawatzke[m has joined #litex
sajattack[m] has joined #litex
alanvgreen_ has quit [Quit: Connection closed for inactivity]
pftbest has quit [Remote host closed the connection]
alanvgreen_ has joined #litex
<alanvgreen_> gatecat: Makes sense, thanks for the explanation
<alanvgreen_> _florent_: Thank you for the pointers to the bist function and fifo depth parameter!
pftbest has joined #litex
Coldberg has quit [Ping timeout: 268 seconds]
lkcl has quit [Ping timeout: 265 seconds]
lkcl has joined #litex
<Melkhior> _florent_: is there some documentation explaining the sdram initialization process ?
<Melkhior> Trying to understand it, but in 'sdram_write_latency_calibration' I have test 'if (_sdram_write_leveling_bitslips[module] < 0)', and that global array is never initialized in my case (SDRAM_PHY_WRITE_LEVELING_CAPABLE is not set)
<Melkhior> So the array sould be all-O (it's a global), so the test is always false, so 'bitslip' is always set to the array content, i.e; to 0 ... making the test loop somewhat redundant
<Melkhior> Must be missing something ...
awordnot has quit [Ping timeout: 265 seconds]
awordnot has joined #litex
FabM has quit [Quit: Leaving]
Coldberg has joined #litex
alanvgreen_ has quit [Quit: Connection closed for inactivity]
OmkarBhilare[m] has joined #litex
<OmkarBhilare[m]> Hello,
<OmkarBhilare[m]> I wanted to use litedram core in my Google summer of code project under beagleboard org.
<OmkarBhilare[m]> The project is BeagleWire Software. The BeagleWire is a FPGA cape for beaglebone black based on iCE40HX. The cape has 32 MB SDRAM. I wanted to produce standalone verilog code for SDRAM controller without the CPU. I have been exploring the litedram but had couple of doubts related to it.
<OmkarBhilare[m]> Can I ask my doubts here?
aquijoule_ has quit [Quit: Leaving]
aquijoule_ has joined #litex
aquijoule_ is now known as richbridger
richbridger has quit [Remote host closed the connection]
richbridger has joined #litex
<jevinskie[m]> Yes please. Don’t need to ask to ask :)
<OmkarBhilare[m]> Actually my rest of the Designs were in Verilog. So I wanted to produce standalone verilog code with CPU as none.
<OmkarBhilare[m]> So wanted to ask does litedram can produce the core without the cpu, just exposing the wishbone will do.
<OmkarBhilare[m]> For standalone I was looking into this.
<OmkarBhilare[m]> I see some yaml examples here
pftbest has quit [Remote host closed the connection]
pftbest has joined #litex
pftbest has quit [Remote host closed the connection]
alanvgreen_ has joined #litex
TMM_ has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM_ has joined #litex