12:31 <Melkhior> for those interested, Litex now has support for an USB OHCI host controller using a SpinalHDL implementation (same source as VexRiscv)

12:31 <Melkhior> It works with 1 to 4 ports (at least!) using a purpose-built pmod, again from the same source: https://github.com/Dolu1990/pmod_usb_host_x4

12:35 <ysionneau1> that's a really cool news :)

12:45 <Leon[m]> Indeed very cool

12:45 <Leon[m]> If only SpinalHDL would be more than a magic black box for me

13:06 <Melkhior> @Leon[m] SpinalHDL is easier to deal with than VHDL/Verilog :-)

13:07 <Melkhior> USB OHCI is here: https://github.com/SpinalHDL/SpinalHDL/tree/dev/lib/src/main/scala/spinal/lib/com/usb

13:09 <Leon[m]> Melkhior: I think what's easiest is what you're used to... I taught myself a bit of VHDL and can figure out where to go from there. I've spent hours over the VexRiscv implementation and only ever randomly type things I don't understand to wind up with Scala compiler errors.

13:10 <Leon[m]> Maybe I just need to get over that critical point where I understand more significant parts of the code.

13:13 <Leon[m]> Melkhior: did you know Scala when starting with Spinal?

13:16 <Melkhior> Leon[m]: no no scala, just a bit of VHDL for a crazy project (https://github.com/rdolbeau/SBusFPGA)

13:16 <Melkhior> Just did a bit of SpinalHDL to extend the core with new instructions (https://github.com/rdolbeau/VexRiscvBPluginGenerator)

13:18 <Melkhior> And Migen only for the board/target support and porting a PS2 controller from Verilog to Migen (now somewhat obsoleted by Dolu1990 OHCI controller...)

13:18 <Melkhior> And you're right, easiest is what you already know :-)

13:19 <Melkhior> Though I am thinking of redoing my SBus stuff in Migen, hoping to have a shot at a SBus <-> Wishbone bridge and maybe being able to leverage the Litex peripherals in a SPARCstation :-)

13:19 <Leon[m]> Very cool

16:07 <Melkhior> Dumb question on FPGA; can warming up changes their behavior ?

16:08 <Melkhior> my litex soc works fine, but I had some weird errors - a benchmark was (deterministically) failing, despite being the same binaries that was working before

16:08 <Melkhior> I let the board cool down (and I do have an extra heatsink on the FPGA), then restarted -> now it works fine

16:09 <Melkhior> a previous power-cycle (where the fpga was still warm-ish) had not cleared the issue...

16:10 <Melkhior> it seems to be memory-related; could the litedram controller or the on-board dram be affected by heat ?

16:10 <Melkhior> (the heat-sink is not hot, just warm-ish)

16:14 <acathla> Melkhior, I think the litedram is doing some auto-config at start

16:18 <_florent_> Melkhior: this could impact the DRAM timings a bit yes but we generally have some margin on Artix7. That would be useful to share your DDR3 calibration log (and temperature during the benchmark)

16:19 <_florent_> you can get the temperature with the XADC: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/xadc.py

16:30 <shoragan[m]> does anyone have an idea where should i look if i get "bios.elf: error: PHDR segment not covered by LOAD segment"? is the bios too large?

16:30 <acathla> _florent_, some time ago you told me to comment the part in soc.py that reboots the soc controller when the CPU reboots

16:30 <acathla> # Connect SoCController's reset to CPU reset.

16:31 <acathla> It doesn't seem to work anymore

16:31 <acathla> the reboot command (in LiteX's bios) freezes everything

17:09 <Melkhior> _florent_: running on a loop, back to temperature, everything still fine...

17:10 <Melkhior> maybe it's something else

17:10 <Melkhior> will have to investigate how to add the XADC stuff & read the temperature in Linux

17:10 <Melkhior> I hate heseinbug...

17:11 <Melkhior> heisenbug

20:30 <_florent_> acathla: your issue is probably similar to this: https://github.com/litex-hub/litex-boards/commit/bf123db20be8fe90d4dee2ff629f69b748645049, you can disconnect self.rst from the PLL reset

20:32 <_florent_> The behaviour is probably specific to iCE40, I'll try to fix it soon