_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<Melkhior> @_florent_ @somlo yes the USB host in Litex is great, you will still need some way to connect the wire to a USB connector though
<Melkhior> @Dolu1990 has a Pmod in the work: https://github.com/Dolu1990/pmod_usb_host_x4
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<_florent_> Melkhior: Yes we should produce some PMOD for this, but without PMOD it only requires 2 pull-downs on DP/DM. I tested it with this: https://twitter.com/enjoy_digital/status/1397470599262482433
<_florent_> nickoe: you have to use ClockDomainsRenamer, you can grep this in the code base
<nickoe> mmm
<nickoe> _florent_: what should I assign it to?
<nickoe> _florent_: I want the FSM in this module to run with another clock domain than sys. https://github.com/nickoe/litex-boards/blob/4f766b4fb8080d7073017a055008185aa99dd1c3/litex_boards/targets/mars_ax3_custom.py#L246 The clock domains is defined externally.
<nickoe> so I add ClockDomainsRenamer before/around my actual instiation of my module?
<nickoe> I thought I could define it inside the module.
<Melkhior> @_florent_ neat! I'll try to test the core in Litex this week-end. I have a B-optimized Chocolate Doom I want to try - hopefully my compiler patch didn't break the binary.
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