<gatecat>
doing the emulation in M-mode would be cleaner
<tnt>
gatecat: Oh nice, thanks !
<tnt>
ATM I'm just trying to get things vaguely doing something ... but DCache is too large and AFAICT Vex doesn't support AMO without DCache.
<leons>
I've been working on getting LiteX to work on some FPGA board, and unfortunately I'm again at the point where I have issues with DRAM and no clue really on how to diagnose these.
<leons>
Weirdly enough, my DRAM memory seems to work but the memtest is still "KO"
<tnt>
"best: m2, b04 delays: -" sounds bad to me
<tnt>
looks like one of the group failed training
<leons>
tnt: Ah, right, I see that now. I should probably check the constraints then, right? Is there any signal to watch out for specifically?
<tnt>
DQS maybe.
<tnt>
but really I think a wrong DQ would also cause it so .
<gatecat>
yeah
<gatecat>
DQS, DQ and DM
<gatecat>
for m02, the third group
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<leons>
Woah cool, the second DRAM module works perfectly! Will check the constraints of the first now.
<leons>
It's really tedious so I've been whipping up a small python script to translate the MIG XML files to LiteX constraints :)
<leons>
With at least one of my DRAM modules running, I'm reaching speeds of approx. 30MiB/s write and 26MiB/s read. The reference of my FPGA board claims that the DRAM can run at 800MHz and my board features a 233.3MHz clock signal to be used by the MIG. Does LiteDRAM support running the memory at higher speeds, through an external clock?
<_florent_>
leons: The speed reported by the BIOS is the speed seen by the CPU (with the CPU/Wishbone being the bottleneck)
<leons>
florent: Ah, right, I suspected that already
<_florent_>
if you want to test with a hardware generator/check, you can enable the BIST module by setting with_bist=True in add_sdram
<Melkhior>
One Vexriscv can't saturate anywhere near DDR3 bandwidth, even using native interface (i.e. not going through Wishbone)
<Melkhior>
I've seen 100+ MB/s with 4 cores using 1 (shared by 4 cores) or 2 (shared by 2 cores each) FPUs on the 'normal' STREAM benchmark (which is using FP64)
<Melkhior>
And even 170+ MB/s using hand-tuned assembly in the critical loop
<Melkhior>
That's with a 100 MHz sysclk and a 16-bits device (400 MHz DDR3)
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<leons>
Melkhior: thanks for the pointer! I'm still pretty new to this stuff...
<leons>
Eventually I'd like to access the memory in hardware anyways, but for now it's a good first milestone to get the memory working at all :)
<leons>
With AXI lite I'm getting about 600MiB/s in both directions, which isn't too bad but nowhere near the theoretical limit
<leons>
(That's in hardware of course, with `sdram_bist`)
<Melkhior>
Hehe, yes I also have a 'big' one but it's for work only :-)
<Melkhior>
Fun stuff can make do with an Artix-7
<leons>
Absolutely.
<leons>
_florent_: Is a basic SoC with UART, LEDs, Buttons and one of the SO-DIMMs sufficient for an initial upstream already or should I try to get both memories and the Ethernet working first?
<leons>
I'm also thinking about trying to wire a MIG-generated memory up to the AXI lite bus, just to find out whether my hardware is borked or I'm doing something wrong with LiteDRAM (probably the latter)
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