06:25 <Melkhior> _florent_: in the DDR3 gist you posted, the code assumes you already know the timings needed if I understand correctly ? bitslip and delay are hard-coded

06:58 <_florent_> Melkhior: yes exactly, I was using fixed bitslip/delays (the one knowing to work with the BIOS)

06:59 <_florent_> we have enough margin to have something usable

07:00 <Melkhior> _florent_: would that work per-design ? I.e. if you calibrate on a specific board, would that still work on a different board of the same make and model ?

07:00 <_florent_> and that's also used by some vendors

07:03 <_florent_> Melkhior: the variation between boards should be negligeable vs the margin we have, so once calibrated on a board, it should work on other similar boards (On Digilent Arty it was the case)

07:03 <Melkhior> OK thanks

07:03 <Melkhior> Just writing values if Forth should be much easier than trying to implement all the testing loops...

07:04 <Melkhior> Although nothing is going to use the SDRAM before the OS has booted on the host anyway :-)

07:06 <Melkhior> Swapping to the FPGA DDR3 controller by litedram with a custom DMA talking to LiteDRAM{Reader,Writer} is a lot faster than swapping to a micro-sd card on a SCSI2SD V6 behing the ESP SCSI controller!

07:07 <Melkhior> Glad I switched from my home-grown VHDL to a Litex SoC and Migen :-)

07:07 <Melkhior> thanks again !!!

08:16 <_florent_> Melkhior: I think I had also had a simple python script to do the DDR3 calibration and find the bitslip/delays over UARTBone, I'll try to find it

08:22 <_florent_> Melkhior: found it, I added it to the gist: https://gist.github.com/enjoy-digital/529a4d9994f0cc95e45382e4eb253b09#file-test_sdram_init-py

08:23 <Melkhior> thx

08:23 <_florent_> So I was using this script to find the bitslip/delays values to use with the SDRAMInit module on Arty

12:28 <leons> Can I expect any persistent damage to my Xilinx Kintex7 FPGA if I choose the wrong speedgrade while building the bitstream?

12:28 <gatecat> nope

12:29 <gatecat> if you chose a speedgrade lower than the actual one, then there won't be a problem at all

12:29 <gatecat> if you choose one higher than the actual one, there's a possibility at worst the design won't work or will be unreliable

12:29 <leons> lower, meaning slower, meaning higher number? I don't really get Xilinx's logic there...

12:30 <gatecat> a lower speedgrade is slower in Xilinx land

12:30 <gatecat> yes this is the opposite to DRAM etc

12:30 <leons> Ah, okay. I thought I ready somewhere lower number = faster, but that's good to know

12:31 <gatecat> I think that might be in Intel land

12:31 <gatecat> both Lattice and Xilinx have speedgrade being lower=slower

12:31 <leons> I'm trying to prepare a patch to port LiteX to some FPGA board where the documentation does not mention the speedgrade anywhere

12:32 <leons> So I've been just using -1, given I didn't have physical access to the FPGA

12:32 <gatecat> yeah, that's fair

12:32 <leons> And I was wondering whether different production runs of the board might have a different speedgrade

12:33 <leons> Oh, now I'm really confused: xc7k325tffg676-1, is that Speedgrade "1" or "-1"? In the sense would "-2" be a higher or lower number? :D

12:34 <leons> As in: is it a signed integer? :)

12:34 <gatecat> no, it's not signed

12:34 <gatecat> the dash is a separator not a minus

12:35 <leons> Ah, okay, thanks for clarifying!