_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tpb> Title: How to fit 100x RISC-V cores into an FPGA | aignacio (at aignacio.com)
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<_florent_> mithro: thanks, I also discovered this a few days ago. The NoC part seems really interesting
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<chiefwigms> any luck w/ ultrascale+ liteeth?
<chiefwigms> :)
<OmkarBhilare[m]> Do we have any Cpu Non litedram example with external initialization?
<OmkarBhilare[m]> * Do we have any Cpu None litedram example with external initialization?
<mithro> chiefwigms: I would have thought someone had already done that?
<chiefwigms> _florent_ added some code a few days ago, (i tried testing it with a kcu116 and autogenerated code that I had) - but it seems like nothing gets added in the device tree source for new eth phys
<chiefwigms> not sure if that is the only issue, or if more work needs to be done getting the core up as well
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<_florent_> mithro: chiefwigms want to use 1000-BaseX on a Ultrascale+, 1000-BaseX has only been validated on 7-series and Ultrascale for now
<_florent_> I just did a skeleton a few days ago: https://github.com/enjoy-digital/liteeth/commit/2f4964cf56fd5258eda21448269924da0821bfca and verified compilation but haven't been able to investigate further
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<Melkhior> <OmkarBhilare[m]: what do you mean, initiliazing litedram without a CPU in the SoC ?
<_florent_> Melkhior: With SDRAM the initialization is very simple (just a few MR registers to write) so the CPU doing the initialization can be easily replaced with a simple FSM doing Wishbone accesses to the DFI interface
<OmkarBhilare[m]> Where can I find more info on these MR registers?
<_florent_> Generally the CPU is used after the DRAM initialization to run software, so comes for free for the intialization, but when the CPU is only used for DRAM init, it could be interesting to replace it with an FSM
<_florent_> OmkarBhilare[m]: Here is some code I was using for this (but for DDR3 with fixed bitslips/delays for the read leveling): https://gist.github.com/enjoy-digital/529a4d9994f0cc95e45382e4eb253b09
<_florent_> It should be easy to adapt it to SDRAM
<_florent_> You mostly have to adapt the init sequence
<_florent_> you can generate the init sequence as pseudo code with this: https://github.com/enjoy-digital/litedram/blob/master/litedram/init.py#L821-L846
<_florent_> sorry I have to go
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<Melkhior> _florent_: you mean non-DDR sdram right? DDR3 is not so trivial... I tried porting the BIOS code to Forth (for OpenBoot/OpenFirmware) but have yet to succeed
<Melkhior> I have fallen back of regular C code in the OS driver (as it's used as a peripheral by another host)
<Melkhior> Oh, that gist is for DDR3... i'll have to look into that
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<Guest12> Are there any limitations on the refresh interval in litedram? I've made some changes to tREFI that apparently are being ignored
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<leons> I have an FPGA board which has some logic level converters on IOs such as the UARTs. I'm currently just initializing (setting IO directions and output enable) in the BaseSoC construtor in the target file
<leons> Is that the right place to do this or is there some better way?
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