_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> chiefwigms: I just prepared the Ultrascale+ GTYE4 BaseX PHY: https://github.com/enjoy-digital/liteeth/commit/2f4964cf56fd5258eda21448269924da0821bfca
<_florent_> it compiles fine but does not yet seems to be working. I'm not able to spend more time on it now, but maybe you could try it on your hardware
<chiefwigms> sure
<chiefwigms> i'll compare it with mine - for whatever reason, it kept saying one of the clocks wasn't routed completely
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<_florent_> chiefwigms: Ah, I also had this issue and connected the refclk to the GTGREFCLK to avoid it: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/usp_1000basex.py#L611
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<chiefwigms> compiled for me, but when i load a target (kcu116) w/ ethernet, it only shows lo and sit0 on ifconfig
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<OmkarBhilare[m]> Where I can find the info about the inputs in the yml file like supported device, sdram module etc
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<OmkarBhilare[m]> okay got the ram which I wanted
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<chiefwigms> any idea on how to troubleshoot?
<_florent_> chiefwigms: I will try to double check the code next week
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<chiefwigms> thanks
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