sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<palmer> aurel32: Greg and Vineet understand that glibc thing, Vineet's going to post a review -- might not be tonight as it's late here
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<aurel32> palmer: thanks, and no worries, it's not urgent
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<Stat_headcrabed> (Possible) the official statement about T-head cores' float probelm: https://github.com/revyos/revyos/issues/17#issuecomment-1865370138
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<sorear> that much is fairly clear from the big table in https://github.com/revyos/revyos/issues/17#issuecomment-1704118202
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