sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<pabs3> bbyoume: the point he makes is a trusted fab isn't enough (and to some extent cannot exist anyway). anyway, agreed more reproducible builds are needed.
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<bbyoume> pabs3: even if you own the fab and record the employees? *and* own all the tiny parts suppliers too? can u link a specific moment(s) in one of these talks where that is explained?
<pabs3> yes. don't have time to go find the talks sorry. there are more links in the chain though, customs at minimum
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<bbyoume> pabs3: no worries, still find that conclusion hard to believe...keep in mind for customs, a large percent of shipping containers never get opened...and there are tamper evident nailpolish techniques that can reassure that some devices or boxes or wtv were never opened
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<jfsimon1981_b> Good morning
<jfsimon1981_b> Getting the CH32V103 devkit to experiment with, neat
<jfsimon1981_b> Shipping in 2 weeks
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<courmisch> yikes. T-Head kernel hits illegal instruction upon entering user space, but only if vector are enabled *and* the kernel is built with an upstream toolchain rather than theirs
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<Tenkawa> Been away a while... hows the 6.7-rc kernel efforts going (specificly on the JH7110 series machines)
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