sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<unlord> woah, that link to a zip instruction is useful
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<courmisch> on simple bswap16, the vwaddu/vwmaccu interleaving trick is slower than bit shift and or
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<dzaima[m]> just shift+or, or zext+shift+or? cause for a vector-vector interleave you need the three
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<courmisch> shift+shift+or
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<courmisch> it's probably an edge case though
<courmisch> also I can see the value of the add/acc trick if you can't spare a vector
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<dzaima[m]> don't find it particularly weird that this'd be the case on some implementations, but this one, going by camel-cdr's benchmarks (https://camel-cdr.github.io/rvv-bench-results/canmv_k230/index.html for those that haven't seen) it'd seem to me that it should be faster? or are the benchmarks not particularly accurate for throughput (perhaps from some hazards due to no register rotation & being in-order)?
<dzaima[m]> oh, misread your shift+shift+or as zext+shift+or; so presumably you're actually comparing vnsrl+vnsrl+vwaddu+vwmaccu vs shift+shift+or?
<courmisch> for a simple bswap16, it's vlseg2e8;vwaddu;vwmaccu vs vle16+vsrl+vsll+vor
<dzaima[m]> ah, so a segment load; how does that alone compare to the vle16?
<courmisch> I didn't take measurement. camel coder seemed to imply that it's about the same?
<dzaima[m]> oh, it's under byteswap benchmarks
<dzaima[m]> oh, no, that's a different thing
<courmisch> it seems he's using byteswap as a way to bench gather
<courmisch> it doesn't make sense to use gather for this in real life, AFAIK
<dzaima[m]> the only thing said there is about segmented stores being about as fast, nothing about loads (though it would be somewhat weird if the two were particularly different)
<dzaima[m]> even then, the segment store version gets to avoid a vzext.vf2 and still ends up slightly slower than the alternative, so it's still looking far from on-par; I think camel-cdr's intent is that it's just closer to a vector load than scalar loads (which is the case on the C920 0.7.1 tests)
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<dzaima[m]> (s/is/isn't/ perhaps; C920 0.7.1 segmented stores are worse than even the scalar comparison, I mean)
<dzaima[m]> (that s/is/isn't/ being on the second "is" in my message)
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<unlord> dzaima[m]: thanks for the link, I had not seen those benchmarks
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<courmisch> is it just me or RDTIME and RDCYCLE (subtractions) don't always give proportional values on K230?
<courmisch> is there some frequency scaling? which metric should be used for microbenchmarks?
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<courmisch> https://paste.debian.net/1297899/ <- anybody understands why this causes an illegal instruction on C908?
<courmisch> looks like CPU bug to me
<courmisch> I would understand "e32, mf8" or "e64, mf4" crashing but ?!
<dzaima[m]> e32 mf4 is invalid
<courmisch> is it? a quarter of 128 bits is 32 bits
<dzaima[m]> fractional LMUL is only allowed to be as little as needed for being able to widen to e64 ≥m1
<courmisch> then it's a QEMU bug
<dzaima[m]> that sounds possible
<sorear> are you sure this isn't a reserved encoding and qemu can't handle it arbitrarily?
<courmisch> that could be
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<courmisch> sorear: I can't find where that's explained. It's alluded to in the table in §4.4
<courmisch> ah §3.4.2
<dzaima[m]> "For a given supported fractional LMUL setting, implementations must support SEW settings between SEWMIN and LMUL * ELEN, inclusive."
<courmisch> so it's allowed to either work , or set the vill bit
<courmisch> would be nice if QEMU had a switch for this
<courmisch> okay nvmd then
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