<conchuod>
The other patch in that series seems pointless atm, it has no actual user?
<conchuod>
The bit of code you're pointing out is a single wrote (per hart) during boot. In my naivety that seems okay.
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<palmer>
deepak is working on CFI stuff, so I bet there's something related going on
<palmer>
is there maybe now a user-mode writeable envconfig of some sort?
<palmer>
I guess maybe just post on the thread? I'll have time to look eventually...
<conchuod>
he should sent the patch when he has a user
<conchuod>
s/sent/send/
<palmer>
I generally agree, but if some extension has added user-mode writeable envconfig bits then I think we just ended up with a backdoor user? probably best to ask on the thread, though
<palmer>
it should at least be called out, and I guess in theory gated behind whatever extension needs it (though with just the single CSR write maybe gating it is overkill)
<palmer>
I'm not really a KVM guy, though, so I might be off there
<sorear>
me neither, looks plausible
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<pepperoni>
considering a gentoo install on a beaglev-ahead board w/ a 6.1 kernel. Anyone know of issues why this wouldn't work?
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<palmer>
drewfustini: ^
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<palmer>
pepperoni: looks like Drew might be away, but I'd guess that 6.1 i a bit too old for the BeagleV. It's a pretty new board, and things move super fast in RISC-V right now. I see the DT in 6.6: https://kernel.dance/#31ceedee8aa4559494d2ebb85c484efff6f5afa1
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<drewfustini>
Thanks for the ping. The vendor only supports 5.10. people in the community have been trying to get support into mainline.
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<drewfustini>
6.6 can boot to a shell. 6.8 will support eMMC
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<sorear>
Is it publicly known whether the U74, U54, or C908 comply with Ztso?
<sorear>
(it'
<sorear>
(it's a generic property of in-order cores with sufficiently simple cache systems, and one that software would like to know about if true)
<muurkha>
always nice when you can add an instruction set extension without adding any instructions or transistors
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<fredholmes>
please tell me about the masking of memory(word addressable) to implement store byte? Is it necessary to mask the memory or is there any other method?
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<geertu>
muurkha: ... even when adding a RISC-V extension to non-RISC-V CPU cores ;-)
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<muurkha>
geertu: haha
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<Esmil>
a
<Esmil>
dlan: Do you know what the state of u-boot for the Lichee Pi 4A is?