sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<geist> yeah i guess it's the lack of a general instruction form with a 16bit constant field. if it had it then it's very natural to have a load immediate slot 1 2 3 4 instruction (a la arm64)
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<courmisch> you can assign a 64-bit value with up to 5 insns. it's not much worde than arm64's 4 insns
<courmisch> worse*
<courmisch> and unlike arm64, there is an official pseudo insn so you don't need to define a custom macro in every project
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<dh`> it's 5 only if you have a scratch register
<dh`> anyway, iirc on sparc sethi doesn't change the rest of the register (the usual sequence is ori then sethi, rather than lui followed by ori or addi(u))
<dh`> and one of the reasons for that is that like riscv the high part is large
<dh`> but I could be misremembering
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<drmpeg> Here's some SPARC code. https://www.w6rz.net/sparc.png
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<courmisch> well it's 8 insn if you don't but then again, most often you do, or you can load from literal pool in two insns
<courmisch> size wise it's 6.5 insns as 3 of the 8 are compressible
<courmisch> but point taken
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