sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
<palmer> IDK what else to do with times, though, it's kind of the only option for everyone
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<dh`> in netbsd there is no possible time that isn't absolutely awful for a significant number of people
<dh`> it's an intractable problem
<palmer> yep, and 7am pacific is bad for pretty much everyone ;)
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<dh`> nah, it's midafternoon in europe
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<kilobyte_ch> Hi, I'm trying to use FreeRTOS on a WCH CH32V307. The Vendor example in the Vendor IDE works (https://github.com/openwch/ch32v307/tree/main/EVT/EXAM/FreeRTOS/FreeRTOS). I ported the Vendor example to a Makefile which also uses again the Vendor Toolchain. It builds fine, but when doing a xTaskCreate it fails with a HardFault. The HardFault indicates an Illegal Instruction. Any idea what the issue could be?
<kilobyte_ch> Call stack to the HardFault https://ibb.co/5R7s9pD
<kilobyte_ch> I guess the issue is the following asm instruction, but I have no idea why this is an issue https://github.com/openwch/ch32v307/blob/main/EVT/EXAM/FreeRTOS/FreeRTOS/FreeRTOS/portable/GCC/RISC-V/portmacro.h#L109
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<palmer> kilobyte_ch: that's a M-mode instruction, are you running outside of M-mode?
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<tusko> What is the most painfree way to load a 32-bit number into a register. Is there a macro or do I need to load an immediate and shift
<la_mettrie> load upper 20-bits with LUI and then the rest with ADDI
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<tusko> thanks pimp
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<palmer> There's a "li" macro is most assemblers
<tusko> Yeah, the thing is I'm bulding a processor so I'm not 100% sure I have li implemented
<tusko> I'm just a low monkey on the tree
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<jrtc27> li is a macro not an instruction
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<tusko> Right, but if I didn't implement it in the processor...
<jrtc27> I don't think you understand what macro means
<jrtc27> it is not an instruction
<jrtc27> you do not implement it in the processor
<jrtc27> the assembler converts it into a series of real instructions
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<jrtc27> e.g. li with a signed 12-bit value will just be addi rd, zero, imm
<tusko> I'm not sure you understand that I am implementing a risc-v processor from scratch. I have implemented every instruction that it knows about (add, addi, ...)
<tusko> How will it know such a macro exists if I never told it?
<geist> because the macro isn't an instruction the cpu runs. it's a directive to the assembler to generate other instructions
<geist> so if you implement the instruction the macro expands to, then you've got it
<tusko> I see, yeah I guess I don't understand it exactly
<tusko> I assumed I was building the assembler, somehow
<tusko> It sounds to me, based on what you guys are saying, the assembler is somehow already existing
<geist> of course. it's a piece of software that exists in many forms already
<geist> same as compiler, or any other riscv software
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<dh`> I see we have much more of an assembler manual now, cool
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