sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv
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<pabs3> bjdooks: thats a bug in readline, affects all arches (and bash has an embedded code copy of readline, so it needs fixing separately)
<pabs3> the bash version in Debian testing works, so you could rebuild that on riscv64 to get bash working
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<rneese> for those of you who might to join us on discord
<rneese> here is a inite
<rneese> invite
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<ornx> is there a better implementation of 64-bit li for arbitrary constants than https://paste.debian.net/1257772/ ?
<ornx> (using only RV64I)
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<ornx> hm wait i think i have an extra 4 bits im not using per ori
<dh`> indeed
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<dh`> though don't forget sign extension
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<geist> that sequence seems way more work than it should
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<geist> generally worst case you need a two instruction lui; addi
<jrtc27> how are you getting 64 bits into 20+12=32 bits
<ornx> you can also only use lui once, it sign extends the upper 32 bits
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<muurkha> geist: for RV32
<muurkha> ornx: have you thought about putting your 64-bit constant in a constant pool?
<muurkha> then you can load its address with an la (auipc+addi) and then a load
<muurkha> loads the constant
<jrtc27> use lla, you don't want to pick up the unnecessary GOT indirection here if built with -fPIC
<muurkha> oh thanks jrtc27!
<ornx> i wanted to write my own li as a learning exercise, so i didnt consider the case of actually loading it with a load instruction
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<geist> Oh yeah duh, forgot about rv64
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<dh`> I'm still sort of surprised rv64 didn't get an instruction that pastes bits 12-31 without affecting the rest
<dh`> but I suppose fully general 64-bit constants aren't actually an important target
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