12:12 <tnt> Is the PCIe core supposed to downgrade link width automatically ? (i.e. a 4x core plugged in a 1x slot will automatically negotiate 1x). I know the standard defines it as such, but not sure if it's implemented/tested.

13:06 <tnt> Answering my own question: yes, it should.

18:30 <tnt> My notes so far on what I observed: https://gist.github.com/smunaut/933c674bce9301fee8fa85f224670705

19:16 <cr1901> _florent_: https://twitter.com/enjoy_digital/status/1496192342793064448 How did you get 10x+ write speedup and 6x read speedup :o? I didn't think WB burst alone would allow that sort of speedup