_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<tnt> Is the PCIe core supposed to downgrade link width automatically ? (i.e. a 4x core plugged in a 1x slot will automatically negotiate 1x). I know the standard defines it as such, but not sure if it's implemented/tested.
<tnt> Answering my own question: yes, it should.
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<cr1901> _florent_: https://twitter.com/enjoy_digital/status/1496192342793064448 How did you get 10x+ write speedup and 6x read speedup :o? I didn't think WB burst alone would allow that sort of speedup