_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://libera.irclog.whitequark.org/litex
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<_florent_> tpw_rules: with Vivado 2018.2, make sure the pcie_s7.xci hasn't been updated with your previous attempts with a newer version of Vivado (so just make sure to revert all eventual LitePCIe changes)
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<pftbest> _florent_: Hello. I am trying to port litex to a new Kintex 7 board, but I have some issue with DDR3. It behaves randomly, sometimes it works and passes memtest but sometimes it fails
<pftbest> For example https://dpaste.com/DNERCLY3H.txt
<pftbest> In this log first it works fine, then I type reboot and it fails
<pftbest> Can you give some hint why it may behave this way?
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<Melkhior> pftbest: in your second part (where it fails), m2 it picking b03 delays: 07+-00
<Melkhior> but the seventh value on line b03 is a zero
<Melkhior> the pattern looks weird - I think the BIOS code expect the 1 to be contiguous and pick the median between first and last
<Melkhior> so with such a pattern of alternating block of 0 and 1 (not-working and working), the BIOS might get confused
<pftbest> hm, do you know what can cause zeroes to appear here&
<Melkhior> normally 0 is when there has been an error, I believe
<Melkhior> so it goes a bunch of wrong timings (zeroes), a small number of OK timings (1), then more wrong timings (more 0)
<Melkhior> and the BIOS picks the middle of the sequence of 1
<Melkhior> but in your case it doesn't do that - no idea why, not an expert
<Melkhior> but that probably explains why it sometimes work and sometimes not
<Melkhior> I would expect the pattern to look more like those in <https://gitmemory.com/issue/enjoy-digital/litex/890/826936087>
<tpb> Title: Pull request #884 seems to break nexys video sdram - litex (at gitmemory.com)
<Melkhior> (even though that's for an issue, the pattern looks OK)
<pftbest> I see, thanks
<Melkhior> Maybe the memory is run too slow ? Kintex 7 are fast (and probably could take DDR4 instead of DDR3)
<Melkhior> I had some issue at one point with a too-slow system causing memory issues...
<pftbest> in my case the memory is on a sodimm module DDR3-1066
<Melkhior> perhaps try with 125 or 150 MHz sys_clf_freq
<Melkhior> s/clf/clk/
<pftbest> So my options are 100 125 and 133
<pftbest> but in my tests it seem to behave worse on higher frequencies
<Melkhior> You have outside constraints ? (Litex should be able to configure any sys_clk_freq)
<Melkhior> (though sometimes you need multiple PLLs for various clocks if their frequency relationship is weird)
<Melkhior> ouch
<pftbest> well, any frequency from 100 to 133 should work I think, but those 3 I tried so far
<pftbest> 133 is the max because the memory is 1066
<Melkhior> You have a L2 in there, could be a source of trouble (including endianess issue in the framebuffer), maybe try without it...
<Melkhior> the L2 forces the use of a Wishbone interface instead of the direct access
<Melkhior> shouldn't affect the BIOS 'training', but you never know ...
<Melkhior> might be worth a try...
<pftbest> I tried to set it to 0
<Melkhior> Beyond that sorry I don't know :-(
<pftbest> It didn't help unfortunately
<pftbest> I can try to modify bios to make it find the longest sequence of 1
<Melkhior> Yes, but that might be a symptom of something else
<Melkhior> Hopefully _florent_ will have better suggestions
<Melkhior> Good luck...
<pftbest> Melkhior: but it won't help in this case https://dpaste.com/8ZVFACMZD.txt
<pftbest> where I get no 1 at all
<pftbest> I'm not sure how it can vary so much between reboot
<Melkhior> yes, no 1 is definitely bad...
<Melkhior> The lack of 1 after 'Cmd/Clk' is also suspicious
<pftbest> Do you know what is "Cmd/Clk scan"?
<Melkhior> no, don't think my board did that
<Melkhior> it's definitely in the BIOS
<Melkhior> in sdram_write_leveling
<Melkhior> maybe you can try a wider range than 0-16 and see what happens ?
<Melkhior> You can also try to set SDRAM_WRITE_LEVELING_CMD_DELAY_DEBUG, maybe it will suggest something...
<Melkhior> Seems your issue is above my skill level, sorry :-(
<pftbest> Melkhior: I looked at the datasheet for my memory http://88.99.85.67:1337/Screenshot%202021-08-27%20at%2018.48.39.png
<pftbest> Maybe I have to change CL CWL
<pftbest> Or try sysclk lower than 100
<pftbest> because with CL-6 CWL-5 it seems 100 is an upper limit
<Melkhior> Yes you could try 7/6, it the 2.5/3.3 is the min/max cycle time then it's 300->400 Mhz and with 100 Mhz sys_clk, the 4x is at 400 Mhz
<Melkhior> 90 MHz would be in the middle of the range for 6/5
<pftbest> I'll try
<Melkhior> cl / cwl are in get_ddr3_phy_init_sequence I think (litedram/litedram/init.py)
<Melkhior> mmm, weird that you get 6/5
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<Melkhior> ... but that might be based on the 'live' frequency, not that of the chip
<pftbest> 90MHz 6/5 didn't help: https://dpaste.com/GLAG94UXB.txt
<pftbest> Now will try to change CL
<Melkhior> Interestingly, still loads of 0 for Cmd/Clk, but only 6 taps so something changed
<pftbest> Melkhior: 6/7 still failed but Cmd has more 1 now https://dpaste.com/HQTFM3VYC.txt
<Melkhior> Hehe and you went for higher frequency as well
<Melkhior> m6 is a complete failure though - nothing worked
<Melkhior> I think you should try 7/6 at 100 MHz... but I'm out of my depth here
<Melkhior> Good luck again
<pftbest> I'll try to find a different memory module, maybe the one I have is weird
<Melkhior> Worth a shot if you have other modules handy
<pftbest> I tried 7/6 @100 and it was the same, so I'll go disassemble my old laptop for some memory
<_florent_> pftbest: It seems the write DQ-DQS training is not done correctly on sometimes not done correctly on your board
<pftbest> _florent_: I'll try
<_florent_> otherwise, be sure to configure the correct INTERNAL_VREF or DCI_CASCADE for the DDR3 bank
<_florent_> If you are adapting from the MIG, be sure to use the same IO constraints
<_florent_> Is it your own board or a known development board?
<pftbest> It is HPC-STLV7325. It has a reference design with MIG which works fine
<pftbest> I copied kc705 platform and modified the pinouts
<_florent_> ok, can you share the .xdc for the DDR3/MIG?
<pftbest> sure
<_florent_> ok, so DCI_CASCADE constraint is similar to the KC705
<pftbest> yes, it looks the same, the only difference is DQS pins are DIFF_SSTL15_T_DCI but for kc705 they are DIFF_SSTL15
<pftbest> I tried both but didn't observe any difference
<pftbest> Also VCCAUX_IO is NORMAL in my case
<_florent_> ok, so you can try to disable the Write DQ/DQS training
<_florent_> it's a relatively new features and that's possible some corner cases are not handled correctly
<pftbest> _florent_: I disabled the option but it still fails https://dpaste.com/HCXFQXKVK.txt
<pftbest> _florent_: Is it ok that "Cmd/Clk scan" is mostly 0 ?
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<pftbest> _florent_: I think this is the main issue in my case https://dpaste.com/F2AGR4ULR
<tpb> Title: dpaste: F2AGR4ULR (at dpaste.com)
<pftbest> It set delay to 0 because there was a glitch at the start
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