00:51 <whitequark> kivikakk: yes, actually! how good are you with C++ and Verilog?

00:52 <whitequark> take a look at https://github.com/YosysHQ/yosys/pull/2459; that's the point where I stopped working on it

00:52 <kivikakk> whitequark: C++ good, Verilog a bit of a baby still but I can manage

00:53 <kivikakk> awesome, thanks; will start looking into once I'm done with my current urgent maintainer duties!

00:53 <whitequark> thank you a lot

00:54 <_whitenotifier-9> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/21ae6252e6e5...249e27775222

00:54 <_whitenotifier-9> [YoWASP/yosys] whitequark 249e277 - Update dependencies.

01:18 <_whitenotifier-9> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±2] https://github.com/YoWASP/nextpnr/compare/825a75f2f716...283d538b2f77

01:18 <_whitenotifier-9> [YoWASP/nextpnr] whitequark 283d538 - Update dependencies.

11:05 <d1b2> <dave berkeley> I've added some binary ops on Streams using subclasses (eg MulSigned) to provide a function that does the operation. Using local signed variables in the function. It works fine in simulation. I'm trying to work out a set of primitives required to build DSP blocks - eg multiply and accumulate. Thoughts welcome : https://github.com/DaveBerkeley/streams/blob/master/streams/ops.py

11:49 <d1b2> <dave berkeley> Sorry, meant to tag joshua, but this discord bridge seems to break that.

12:21 <d1b2> <dave berkeley> Yes, of course. How should I go about that?

20:57 <ydnatag> 4:08 AMs#