00:57 <d1b2> <josuah_dem> LectronZ is selling it, but there are a lot and a lot of iCE40 FPGA boards around! https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards

00:57 <d1b2> <josuah_dem> healdove: ^ my bad, my IRC client broke

00:57 <d1b2> <josuah_dem> > thanks for the hard work 🙂

00:58 <d1b2> <josuah_dem> seconded!

04:01 <d1b2> <Nate> getting DriverConflict: Signal '(sig clk_recovered)' is driven from multiple fragments: top.<unnamed #1>, to p.<unnamed #2>; hierarchy will be flattened but I def only have one .eq statement. Is there something special to take into consideration when generating a clock domain from user logic?

04:03 <whitequark> please post your code

13:24 <healdove> josuah_dem: woah that's a great list, thanks!

13:59 <d1b2> <josuah_dem> headlove: I'd consider the iCEBreaker, which would also support the work done here https://github.com/icebreaker-fpga/icebreaker It is also likely to receive support for all the new things first for that reason

14:49 <FL4SHK> I'm gonna go ahead and implement a processor that I have a partial GCC backend written up for

15:09 <Sarayan> sounds fun

21:48 <d1b2> <Nate> I think I figured it out. While making an MCVE I noticed I was appending my module twice, like m.submodules += DomainRenamer(..)(mod) m.submodules += mod hence the multiple drivers