06:07 <_whitenotifier-9> [amaranth-boards] bl0x synchronize pull request #208: Initial support for Tang nano 9k board - https://github.com/amaranth-lang/amaranth-boards/pull/208

08:03 <d1b2> <jer_emy> how do I get access to the amaranth signals that correspond to the module rst signal? I'm trying to basically do m.If(reset):

08:04 <d1b2> <jer_emy> also, how can I get access to the clk signal to add it to my list of traces in the sim.write_vcd call ?

10:07 <vup> @jer_emy: ResetSignal("domain_name") and ClockSignal("domain_name")

10:41 <_whitenotifier-9> [amaranth-soc] chenz opened issue #39: Resources on dense memory windows must be sized multipes of "parent" data_width? - https://github.com/amaranth-lang/amaranth-soc/issues/39

13:14 <DeVector[m]> Catherine: Can you please share CXXRTL testbench for Minerva SoC(https://twitter.com/whitequark/status/1341128583901810693?s=20) if you still have

22:34 <d1b2> <jer_emy> @vup: I tried that, but if I add ClockSignal() or reference the stored clock signal instance inside my class in the traces=[...] parameter of the write_vcd function I just get the error AttributeError: 'ClockSignal' object has no attribute 'name'

22:35 <d1b2> <jer_emy> similar problem for ResetSignal too

22:40 <d1b2> <jer_emy> also, how do you drive ResetSignal in a testbench ? if I try inst.rst.eq(0) I get AttributeError: 'ResetSignal' object has no attribute 'reset'