01:04 <d1b2> <Nate> Would like to perform a simple clock domain rename (before trying more complex things). Trying to simulate with: m = Module() cd_os = ClockDomain("os") m.domains += cd_os dut = DUT() m.submodules.dut = DomainRenamer("os")(dut) sim = Simulator(m) clk_per = 1/clk_freq sim.add_clock(clk_per, domain="os") sim.add_sync_process(run) with sim.write_vcd(f"{type(dut).__name__}.vcd"): sim.run() but getting: File

01:04 <d1b2> "/home/nates/.local/lib/python3.10/site-packages/amaranth/sim/_pycoro.py", line 85, in run raise NameError("Received command {!r} that refers to a nonexistent " NameError: Received command (tick sync) that refers to a nonexistent domain 'sync' fro m process '/home/nates/.local/lib/python3.10/site-packages/amaranth/sim/core.py:90'

01:13 <d1b2> <Nate> oh, I specified domain="os" and it works

01:16 <d1b2> <Nate> random q: any way to shift select a group of signals to add in gtkwave (or some workaround)? Or is it always a recursive append all? 😅

01:49 <kivikakk> Nate: if you specify `gtkw_file="blah.gtkw", traces=[x, y, z]` to the `write_vcd` call, then opening the gtkw file will open the vcd with those traces shown

01:52 <d1b2> <Nate> I guess that’ll work to print them out

13:41 <_whitenotifier-9> [amaranth-boards] chenz opened pull request #220: blackice_ii: fix incorrect SRAM /CE pin assignment - https://github.com/amaranth-lang/amaranth-boards/pull/220

13:42 <_whitenotifier-9> [amaranth-boards] chenz synchronize pull request #220: blackice_ii: fix incorrect SRAM /CE pin assignment - https://github.com/amaranth-lang/amaranth-boards/pull/220

14:09 <_whitenotifier-9> [amaranth-boards] whitequark closed pull request #220: blackice_ii: fix incorrect SRAM /CE pin assignment - https://github.com/amaranth-lang/amaranth-boards/pull/220

14:09 <_whitenotifier-9> [amaranth-lang/amaranth-boards] whitequark pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/amaranth-boards/compare/42152283d98e...892236ade101

14:09 <_whitenotifier-9> [amaranth-lang/amaranth-boards] chenz 892236a - blackice_ii: fix incorrect SRAM /CE pin assignment

15:09 <healdove> definitely off topic Q: (sorry) is there a good basic learners iCE40 board that's available in EU?

15:09 <healdove> upduino is mentioned a bunch but i can't find an eu retailer

15:10 <healdove> icestick is mostly available (at a price) but i like the IO on the upduino

15:18 <whitequark> https://1bitsquared.de/products/icebreaker

15:46 <healdove> oh awesome, cool

15:46 <healdove> thanks!

17:17 <FL4SHK> hello, long time no talk

17:18 <FL4SHK> I read the email sent out from Patreon that the RFC for allowing any combination of composite types is now merged

17:18 <FL4SHK> is that RFC implemented yet?

17:19 <FL4SHK> i.e. is the Python code written

17:44 <whitequark> hi FL4SHK

17:44 <whitequark> yeah, the code is merged as well

17:45 <FL4SHK> hi whitequark

17:45 <FL4SHK> Where can I find it?

17:46 <FL4SHK> oh I can just do a search

17:47 <FL4SHK> ah there it is!

17:47 <FL4SHK> great, thanks for the hard work :)

18:47 <FL4SHK> finally got it working :)