00:00 <d1b2> <jer_emy> does anyone have a small example of how to add and use a verilog file into an amaranth project? I can't seem to find one

00:05 <tpw_rules> https://lab.ktemkin.com/post/nmigen-instance/ this is from back when amaranth was called nmigen but it should still be relevant

00:09 <d1b2> <jer_emy> awesome thanks

01:22 <_whitenotifier-9> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/nextpnr/compare/4d51aad0f7ae...2f8966241cd0

01:22 <_whitenotifier-9> [YoWASP/nextpnr] whitequark 2f89662 - Update dependencies.

08:38 <d1b2> <Nate> probably something silly, but it seems pysim is hanging when m.d.sync += din.eq(self.i_data) logic is hit (runs fine when commented out)

08:41 <d1b2> <Nate> also, probably another easy one --it wasn't immediately obvious to me how/if one can wait for a pulse. Is that done via yield from(...)?

11:27 <d1b2> <tiktik> my ft4232h mini not show eprom

11:28 <d1b2> <tiktik> after drivers update 4 port show

12:49 <bl0x_> Nate: Do you have a combinatorial loop? That happened to me before. Then the simulation just hangs. Yosys will tell you about the loop and then you can fix it.

12:49 <bl0x_> No wait, at least Vivado tells about the loop. Not sure about Yosys now...

12:51 <whitequark> Yosys sometimes does and sometimes does not

12:51 <whitequark> it's one of those things that should be fixed within Amaranth itself. soon™

12:54 <bl0x_> Nate: 'yield from' just continues execution of the other (generator) function until the next yield. This is related to python coroutines and one could write (probably has written) whole books on the topic.

12:56 <bl0x_> If you want to wait on a pulse, you'd continuously (yield your.design.signal) until it goes active. At least that's how I've done it previously. There may be better ways, though.

12:56 <whitequark> at the moment that's the best way

23:43 <bl0x_> Is there an easy way to take a look at the placed cells and nets when using the Vivado toolchain? Or would I be better off importing the generated top.v into a new Vivado project and compile it there?

23:47 <bl0x_> I mean the graphical floorplan of the device with post-route cells and wires.

23:48 <bl0x_> Along the lines of nextpnr GUI

23:49 <whitequark> I think if you run build.sh, it saves a project file you can open with Vivado

23:50 <whitequark> actually, forget the project file; it saves design checkpoints which you can open

23:59 <bl0x_> Great! Now I see it e.g. top_route.dcp ... well only that one actually. But that should have what I want.