Raito_Bezarius has quit [Read error: Connection reset by peer]
Raito_Bezarius has joined #amaranth-lang
<d1b2>
<dave berkeley> I've been playing around with a Stream implementation for a while. I've just added a "dot" output that allows you to automatically draw connection diagrams, as long as you use Stream.connect(src,sink) to connect the parts of your design. It also shows the payload names,when the aren't just "data". This is useful documentation and allowed me to find a connection bug.
<d1b2>
<dave berkeley> I'm using a ulx3s. The ESP32 sends a command to the SPI Peripheral which allows it to write to some control registers. These control a PhaseSource. My sinewave generator is now a swept frequency generator.
<d1b2>
<VA3TEC-Mikek-14362> Hi Dave! this is absolutely Great!!! I would love to use your system for a project I am working on! I would love to see this type of stream drawing software use something like Gnuradio-companion. (Not sure if everyone is familiar with that software) it's open source. But implemented on the FPGA. With digital filtering, etc, etc. Would be SO cool!!! 🙂 Do you have published on a repo? (Again I am still learning amaranth..
<d1b2>
🙂 and would be SO hopeful! ) Thanks, MikeK.
<whitequark>
it's going to be upstream soonish
<whitequark>
Stream functionality has been long planned, but there's some preliminary work to do
<whitequark>
it will be different from Dave's I think
<d1b2>
<VA3TEC-Mikek-14362> I am currently working on the DECA Fpga board trying to get the Audio working, at first local loops back, then later on, digital filtering, So Stream would be absolutely fun! I am following hans's repo. https://github.com/amaranth-farm/deca-usb2-audio-interface 😺
<bl0x>
josuah: thanks for reminding me, I meant to fix this in the earlier examples too. Right now I didn't have the time to backpropagate any fixes.
<d1b2>
<VA3TEC-Mikek-14362> Can I offer any assistance? (again I am new) Is it just a matter of changing from nmigen to amaranth? And making sure all the legacy stuff has been updated? (would that help?)
<whitequark>
it is
bentomo has joined #amaranth-lang
<josuah>
bl0x: my pleasure, thank you for writing this
<bentomo>
Is there an example of how the ports in hierarchical submodules get connected to each other? I'm trying too wrap my head around using amaranth, my background is Verilog, so not a python expert. I'm having trouble figuring out how to take advantage of python to create something like a bus. Something to replace a SystemVerilog interface. I get that I
<bentomo>
can write a python class function to hook up signals by taking advantage of python loops and data structures, but I don't see anyone else doing that. I've looked at the CSR stuff in amaranth_soc but I feel like there are a lot of implicit connections I'm missing. Implicit is OK but I'm having trouble figuring out when/where those connections are
<bentomo>
actually made.
<josuah>
bentomo: still getting used to Amaranth myself, also attracted by the ability to finally have something like Interfaces widely supported.
<josuah>
I think there are a few existing ones declared into the standard library for well-known signals, allowing some conventions across developers... Let me find these.
<josuah>
note that rather than being a Elaboratable, it is a Record.
<josuah>
Not yet on the Docs yet it seems...
<d1b2>
<VA3TEC-Mikek-14362> can ChatGPT help? 🙂
<d1b2>
<VA3TEC-Mikek-14362> jsu a joke
<josuah>
VA3TEC-Mikek-14362: maybe if it could reliably give better insight than confusion, it could, it might boil down to "reliably"
<josuah>
bentomo: bentomo: everything related to memory_map are there to generate a memory map for documentation following how the bus will latter be configured IIRC.
<josuah>
so you may ignore it...
<d1b2>
<VA3TEC-Mikek-14362> The guys over at Litex and Zealous FPGA playing with it, they said that it worked way better than they thought!! it actually impressed them, of the output. But I do agree, it may not get everything right, i can lead to confusion.
<d1b2>
<VA3TEC-Mikek-14362> I am adding the Deca baord to my version of the repo, is that ok, that I add extra and different boards?
<d1b2>
<VA3TEC-Mikek-14362> FYI, OK, I have successfully added the arrow_deca.py updated devices to the amaranth-boards file, audio, i2c, etc. etc. just compiled the blinky example and works fine on the Board from amaranth-boards. next is to go through bl0x's tutorials. 🙂 baby steps...
<bentomo>
josuah ah ok so that minerva example was what I think I was looking for. I had been looking at the memory and bus already but that was just a pure memory module. Something I've always wanted to do was make an axi peripheral generator but gives you special properties for individual bits, such as self clearing, read only, etc. CSRs appear to have
<bentomo>
most of this but as I went up into records I got lost and couldn't figure out how you actually "instantiate" it to generate synthesizable verilog. Thank you for pointing out that example!
<bentomo>
My hope is that I can build modules in individual python files but each module has the test bench and verification built in. Along with appropriate doc strings so documentation generates from each piece. I'd like to REALLY flex the reusability of python and pitch verilog/vhdl out the window.
<bentomo>
Ah ok, that's a good place to check. I do wonder if there's a place to "hang out" and see what people are doing with amaranth. The RFCs look good. I only just barely know how to use irc. lol I was using Rober Baruchs excellent github guide to start with but as well as it's written it's still a little limited on examples.
<d1b2>
<VA3TEC-Mikek-14362> i was using them too!!!
<d1b2>
<VA3TEC-Mikek-14362> Here is good! 🙂
<d1b2>
<VA3TEC-Mikek-14362> I had a really quick Question, please forgive me for my inexperience, but for this CPU, after you create the minerva core, how do you compile code for it? using the Risc32-linux-gnu-gcc-XX compiler, But how it know about which instruction set to use? I see that's it's RV32IM. do you have to specify the specific GCC compiler? (Any info would be great! ) Thanks! MikeK
FireFly has quit [*.net *.split]
DX-MON| has quit [*.net *.split]
DX-MON has joined #amaranth-lang
FireFly has joined #amaranth-lang
FireFly has joined #amaranth-lang
FireFly has quit [Changing host]
<d1b2>
<VA3TEC-Mikek-14362> Hi bl0x, I found an error in your code in section 03_blink_from_rom. You have the LEDs as LED0, and LED1, and the rest LED1. I quickly changed it. and it seemed to work. your blink.py file. I found a few small errrors in other parts of the code. I also added the DECA board that I am working on did you want me to add that too? How did you want me to pass up the fixes? By a Pull request? Anyway it's up to you....
nak has quit [Quit: Bye]
FireFly has quit [Quit: Leaving]
FireFly has joined #amaranth-lang
<josuah>
VA3TEC-Mikek-14362: I think that there are -m flags for specifying which exact arch of RISC-V you can use: `-march=rv32imac`
<josuah>
The above is what worked for me for GD32VF103 for instance (from GigaDevices)
<Sarayan>
bad choice, that arch won't work with minerva
<josuah>
oh wait that was for Clang even!
<josuah>
Sarayan: yes, and wrong compiler too!
<Sarayan>
-target riscv32 -march=rv32im is what I use for clang
<Sarayan>
avoid the 'c', minerva does not do compressed instructions (aka riscv's thumb)