cr1901 has quit [Killed (NickServ (GHOST command used by cr1901_!~cr1901@2601:8d:8600:911:40ab:efe6:2026:d4c2))]
cr1901_ is now known as cr1901
cr1901 has quit [Read error: Connection reset by peer]
cr1901_ has joined #amaranth-lang
josuah has quit [Ping timeout: 268 seconds]
josuah has joined #amaranth-lang
bentomo has quit [Ping timeout: 260 seconds]
Raito_Bezarius has quit [Read error: Connection reset by peer]
Raito_Bezarius has joined #amaranth-lang
<d1b2>
<Olivier Galibert> I'm going to do the synchronous slow version because the project doesn't care, but I'd like recommendations on how to drive a static ram at full speed from a (wishbone) bus
<whitequark>
can you elaborate?
<d1b2>
<Olivier Galibert> The sram is asynchronous, for instance for write you must set and stabilize the address bus, then after that (min=0 but not negative) set ce/we/ub/lb, then wait at least 5ns, drive the data lines, wait at least 3ns, bring ce/we/ub/lb back up, then you can un-hold the address bus afterwards (not before, min=0) and start the next access 10ns after the first
<d1b2>
<Olivier Galibert> let's way the wishbone bus is 50MHz, and that's the main internal clock of the design, how one should go about playing with the signals to avoid CDC issues without immense buffers. We'll say the wishbone bus is the only connection to the sram, no other access
<d1b2>
<Olivier Galibert> how one would go about designing that?
<whitequark>
ahhh I see, basically you are asking for programmable delay lines
<d1b2>
<Olivier Galibert> og.kervella.org/61-64WV25616EDBLL.pdf for the specific sram datasheet (the c5g has the -10 variant), but I suspect it's a general question
<whitequark>
50 MHz is 20 ns
<d1b2>
<Olivier Galibert> possibly yes
<whitequark>
that's so much slower than the typical SRAM that you don't need any additional buffering?
<d1b2>
<Olivier Galibert> yeah, the sram blows the bus out of the water 🙂
<d1b2>
<Olivier Galibert> so ideally it should look zero-delay from the POV of the bus
<whitequark>
> for write you must set and stabilize the address bus, then after that (min=0 but not negative) set ce/we/ub/lb
<whitequark>
ah I see, you need to insert a small delay between A and CE
<d1b2>
<Olivier Galibert> but I wonder how one goes about doing it in a fpga and in amaranth
<whitequark>
which FPGA family is this?
<d1b2>
<Olivier Galibert> cyclone V
<whitequark>
can you link me to the list of CV primitives so I can offer something that works for you?
<whitequark>
I think you need to follow Figure 2 here: chrome-extension://oemmndcbldboiebfnladdacbdfmadadm/https://cdrdv2-public.intel.com/666402/ug_altiobuf-683471-666402.pdf
<d1b2>
<VA3TEC-Mikek-14362> Thanks Josh! Again on the streaming subject, I also came across this repo from Hans. https://github.com/amaranth-farm/amlib he has been a busy boy lately. 🤔 Dave, I hope that you find this link useful! Thanks MikeK
cr1901 has quit [Read error: Connection reset by peer]