whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings on Mondays at 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
<_whitenotifier-9> [amaranth] whitequark closed pull request #757: vendor.xilinx: fix a SyntaxWarning. - https://github.com/amaranth-lang/amaranth/pull/757
<_whitenotifier-9> [amaranth] whitequark commented on pull request #757: vendor.xilinx: fix a SyntaxWarning. - https://github.com/amaranth-lang/amaranth/pull/757#issuecomment-1449145487
<_whitenotifier-9> [amaranth-lang/amaranth] whitequark pushed 1 commit to main [+0/-0/±1] https://github.com/amaranth-lang/amaranth/compare/14e73a73de54...e3e542afff87
<_whitenotifier-9> [amaranth-lang/amaranth] mwkmwkmwk e3e542a - vendor.xilinx: fix a SyntaxWarning.
<_whitenotifier-9> [amaranth-lang/amaranth-lang.github.io] whitequark pushed 1 commit to main [+0/-0/±27] https://github.com/amaranth-lang/amaranth-lang.github.io/compare/7adc788dc7cc...073afba21667
<_whitenotifier-9> [amaranth-lang/amaranth-lang.github.io] whitequark 073afba - Deploying to main from @ amaranth-lang/amaranth@e3e542afff870eecff96f8806beb70b02092654b 🚀
<whitequark> > <@rob_chipflow:matrix.org> could you do something like :... (full message at <https://libera.ems.host/_matrix/media/v3/download/libera.chat/d132d7efee5e1b8f3f8f10ae357d427ac46ed988>)
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<_whitenotifier-9> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/e1e85c61238e...584ce7662aa2
<_whitenotifier-9> [YoWASP/yosys] whitequark 584ce76 - Update dependencies.
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<_whitenotifier-9> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/nextpnr/compare/f8e37631ac81...58b36345a7bc
<_whitenotifier-9> [YoWASP/nextpnr] whitequark 58b3634 - Update dependencies.
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<robtaylor> <whitequark> "> <@rob_chipflow:matrix.org..." <- Just thinking about being able to write that in a more easily parsable way.
<whitequark> parsable for developers or?
<whitequark> you can already extract any subexpression into a variable
<whitequark> so we might not even need any additional features
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<josuah> since a few weeks, I have for personal set-point to get going (as in "get started", and then some) with Amaranth
<josuah> hope to see that happen soon, in the meantime... back to firmware!
<jn> josuah: cheers! have you picked an fpga devboard yet?
<josuah> jn: a few from lattice :)
<josuah> I am a fan of a standard, and an sdio library
<josuah> of course a glassgow too ^_^
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<d1b2> <Olivier Galibert> I need dual port-ram with one port that's read-or-write and the other readonly, and with the ports on different clocks (one at 50Mhz, the other at 12MHz as 148/12). Is that doable? I know the underlying cyclone V supports that at least on its m10ks
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<whitequark> Olivier: I think you should be able to get this with recent Yosys (for Verilog output)
<josuah> ooh, Verilog output, forgot about that for integrating with 3rd-party IDEs!
<whitequark> IDEs specificaly?
<whitequark> * IDEs specifically?
<josuah> whitequark: this is for an upcoming project, so not entirely sure yet: not even for myself!
<d1b2> <VA3TEC-Mikek-14362> This is a little embarrassing, but I am getting this error in amaranth-boards, and I cannot seem to understand it.
<d1b2> <VA3TEC-Mikek-14362> File "/home/mikek/Documents/Cyclone5_SOC/migen_AND_nmigen_TRANINING/amaranth/amaranth-boards/amaranth_boards/arrow_deca.py", line 8, in <module> from .resources import * ImportError: attempted relative import with no known parent package (Amaranth_build_envrionment) mikek@mikek-AERO:~/Documents/Cyclone5_SOC/migen_AND_nmigen_TRANINING/amaranth/amaranth-boards/amaranth_boards$
<d1b2> <VA3TEC-Mikek-14362> I tried to install amaranth-boards, By python setup install command, not sure if that was the correct way or not. Any help would be great! thanks!
<whitequark> that installation method should have worked fine
<whitequark> how are you running the file that gives you this error?
<d1b2> <VA3TEC-Mikek-14362> (Amaranth_build_envrionment) mikek@mikek-AERO:~/Documents/Cyclone5_SOC/migen_AND_nmigen_TRANINING/amaranth/amaranth-boards/amaranth_boards$ python arrow_deca.py Traceback (most recent call last): File "/home/mikek/Documents/Cyclone5_SOC/migen_AND_nmigen_TRANINING/amaranth/amaranth-boards/amaranth_boards/arrow_deca.py", line 8, in <module> from .resources import * ImportError: attempted relative import with no known
<d1b2> parent package
<d1b2> <VA3TEC-Mikek-14362> should i be using python -m arrow_deca.py
<whitequark> python -m amaranth_boards.arrow_deca should fix it
<d1b2> <VA3TEC-Mikek-14362> up one directory.. ok got it thanks!
<d1b2> <VA3TEC-Mikek-14362> :gnu:
<d1b2> <VA3TEC-Mikek-14362> Would it be ok, To create the amaranth Boards file for the LimeSDR_mini_v2 ecp5 FPGA and such?
<whitequark> yep, sounds good
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<Sarayan> whitequark: I'm using quartus for now, I plan to bring mistral/nextpnr/yosys up to speed once I have the stuff working, but I must have it working first :-)
<whitequark> i.e. have up-to-date amaranth-yosys package
<whitequark> Sarayan: no I'm talking about the Yosys invocation required for the Verilog output to be produced that is fed into Quartus
<whitequark> or a system yosys
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<d1b2> <Olivier Galibert> huh, currently amaranth to cyclev is not going through yosys... am I missing something?
<d1b2> <zyp> all amaranth to verilog is going through yosys
<d1b2> <Olivier Galibert> cyclonev that is
<d1b2> <Olivier Galibert> oh, rtlil to verilog is done through yosys?
<d1b2> <zyp> yes
<d1b2> <Olivier Galibert> didn't know that, makes sense in retrospect
<jn> but verilog to bitstream doesn't involve yosys a second time in this case, as far as i've understood it
<Sarayan> Need a structural recommendation. I want to display stuff on the screen, a tilemap for a start, probably a full framebuffer later. Currently I have a minerva cpu, i2c and random stuff on a 50MHz wishbone bus, and next to that a hdmi class with hdmivideo and hdmiaudio under them that handle hdmi, hdmivideo running at 148Mhz, the pixel clock for full hd
<Sarayan> so I need to plonk some ram both on the wishbone and reachable from hdmivideo. I'm not sure how I should go about that so that it's readable
<Sarayan> Global sync is 50MHz
<d1b2> <zyp> how much throughput do you need from the memory to the hdmi core?
<robtaylor> <whitequark> "you can already extract any..." <- ah, perfect
<d1b2> <Olivier Galibert> right now a byte at 148/12 = 12MHz
<d1b2> <Olivier Galibert> ultimately 32 bits at 148Mhz, but that will be with a sdram or a ddr3
<d1b2> <Olivier Galibert> so more complex, so later
<d1b2> <zyp> in that case it could make sense to have a hdmi memory reader core hanging on the wishbone bus in the 50MHz domain, and just pass bytes through an AsyncFIFO to the fast domain
<d1b2> <zyp> i.e. move the memory reading part into the same domain as where the memory will be, so that only the data stream has to cross domains
<d1b2> <zyp> it's much easier to cross domains with unidirectional streams than bidirectional interfaces
<d1b2> <Olivier Galibert> makes sense
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<_whitenotifier-9> [amaranth] slagernate opened pull request #758: add Lattice Nexus vendor platform (using nextpnr-nexus and prjoxide) - https://github.com/amaranth-lang/amaranth/pull/758
<_whitenotifier-9> [amaranth-boards] slagernate opened pull request #216: add lifcl (lattice crosslink-nx) eval board definition file - https://github.com/amaranth-lang/amaranth-boards/pull/216
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<_whitenotifier-9> [amaranth] whitequark reviewed pull request #758 commit - https://github.com/amaranth-lang/amaranth/pull/758#discussion_r1122317008
<_whitenotifier-9> [amaranth] whitequark reviewed pull request #758 commit - https://github.com/amaranth-lang/amaranth/pull/758#discussion_r1122317563
<_whitenotifier-9> [amaranth] whitequark reviewed pull request #758 commit - https://github.com/amaranth-lang/amaranth/pull/758#discussion_r1122317372
<_whitenotifier-9> [amaranth] whitequark reviewed pull request #758 commit - https://github.com/amaranth-lang/amaranth/pull/758#discussion_r1122316690
<_whitenotifier-9> [amaranth] codecov[bot] commented on pull request #758: add Lattice Nexus vendor platform (using nextpnr-nexus and prjoxide) - https://github.com/amaranth-lang/amaranth/pull/758#issuecomment-1450875278
<_whitenotifier-9> [amaranth-boards] whitequark reviewed pull request #216 commit - https://github.com/amaranth-lang/amaranth-boards/pull/216#discussion_r1122319501