whitequark changed the topic of #amaranth-lang to: Amaranth hardware definition language · weekly meetings on Mondays at 1700 UTC · code https://github.com/amaranth-lang · logs https://libera.irclog.whitequark.org/amaranth-lang
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<_whitenotifier-9> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://github.com/YoWASP/yosys/compare/3d9d223f87c1...33693bc8bbaf
<_whitenotifier-9> [YoWASP/yosys] whitequark 33693bc - Update dependencies.
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<d1b2> <Asherah> @marble I don't understand this as much as I'd like to, but these lines might make more sense to you than me (and possibly explain): https://github.com/amaranth-lang/amaranth/blob/fcc4f54367e4931cfb4e13d96de7d32d7f81219d/amaranth/vendor/lattice_ecp5.py#L308-L351
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<daveberkeley> I've been combining VHDL, Amaranth and Litex for a work project. I came up with a way of exporting the Amaranth code as a Python object that allows generated Verilog to be used as a Python class that wraps an Instance(). It simply marks the ins and outs in the code so these can be defined in the interface, plus the ability to export constants. I
<daveberkeley> also expose my Stream objects (my Amaranth Stream implementation). I have to flatten the code and use a naming convention to export these. They can then be requested and connected directly to Litex Streams, eg for DMA. Am I reinventing the wheel? Are there any existing ways of doing this that I've missed?
<whitequark> sort of; you're reinventing it concurrently with me
<whitequark> the upcoming interfaces feature will do that sort of thing natively
<whitequark> (and streams are going to be built based on it)
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<d1b2> <zyp> I've written something similar for orbtrace: https://github.com/orbcode/orbtrace/tree/main/orbtrace/amaranth_glue
<daveberkeley> I have thoughts on both those areas then. I use a renamer() to decorate Signals in a module so they can be fetched and connected. Which means that the Stream objects must have Signals to connect to, which Litex Streams don't have. I'd add "must have actual Signals" to the Stream spec for this reason.
<whitequark> that's the idea, yes; how else would you do it?
<daveberkeley> Lots of Litex objects have Signals which are not part of the Module, so you can't get at them. I suppose I mean that the signals must be part of the class. ie self.rx = Signal(), not a local variable.
<whitequark> oh, yeah
<d1b2> <zyp> in my approach, I don't care about the signal names, my glue logic just keeps a list of amaranth/migen signal pairs to be connected together and just looks up what names they end up with at time of instancing
<d1b2> <zyp> so I can just do wrapper.from_amaranth() and wrapper.from_migen() to convert one kind of signal to the other
<daveberkeley> d1b2 just looking at that. Interesting
<whitequark> (d1b2 is the name of the bridge)
<whitequark> (zyp is the person talking through the bridge, on Discord)
<daveberkeley> okay, thanks.
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<d1b2> <zyp> I think we have similar goals, so if you'd like to collaborate, I'd be happy to split my code out into a separate reusable project
<d1b2> <dave berkeley> Moved to discord. @zyp code looks cleaner than my approach. My code is for a client, so I'd need their permission to share. My Stream stuff might be useful, but it probably won't conform to the plan for Amaranth Streams.
<d1b2> <zyp> being able to convert to and from Litex streams in the same manner is on my roadmap, I'm just waiting for Amaranth streams to be ready
<d1b2> <dave berkeley> Streams are so powerful. I had mux/demux for changing widths, and a cross clock-domain adapter. Plus some test sink/source modules just for unit tests.
<d1b2> <zyp> indeed, most of orbtrace is streams too, which is the reason most of it is still in migen and not amaranth
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<_whitenotifier-9> [amaranth-boards] bl0x synchronize pull request #185: Add support for cmod_a7 board. - https://github.com/amaranth-lang/amaranth-boards/pull/185
<_whitenotifier-9> [amaranth-boards] bl0x synchronize pull request #185: Add support for cmod_a7 board. - https://github.com/amaranth-lang/amaranth-boards/pull/185
<_whitenotifier-9> [amaranth-boards] bl0x synchronize pull request #185: Add support for cmod_a7 board. - https://github.com/amaranth-lang/amaranth-boards/pull/185
<_whitenotifier-9> [amaranth-boards] bl0x commented on pull request #185: Add support for cmod_a7 board. - https://github.com/amaranth-lang/amaranth-boards/pull/185#issuecomment-1443654572
<byteit101> I saw someone use the undocumented .i/.o/.oe for an i2c signal, but I'm getting errors trying to use them. Is this a master-only feature right now?
<whitequark> no, it's been there for a while
<whitequark> can you share the code and the error?
<byteit101> AttributeError: 'Signal' object has no attribute 'i'
<byteit101> self.sda_z = Signal()
<byteit101> self.scl_raw = Signal()
<byteit101> self.sda_oe = Signal()
<byteit101> self.sda_clean = Signal()
<byteit101> self.scl_clean = Signal()
<byteit101> def elaborate(self, platform):
<byteit101> synch = FFSynchronizer(Cat(self.sda_z.i, self.scl_raw), Cat(self.sda_clean, self.scl_clean))
<d1b2> <20goto10> is I/o/oe not on the I2C pins (and are each signals themselves)
<whitequark> you only get i/o/oe if you do platform.request
<byteit101> Ah! Are you sure you won't accept any help on the documentation? Something is better than nothing
<d1b2> <20goto10> Ah thanks
<d1b2> <Olivier Galibert> Hmmm, on discord we've lost the name of who's talking on irc or the other sources, the avatar is still there though
<byteit101> dropping m.domains += ClockDomain("sync", async_reset=True) into my top level removes the clk and rst signals from the verilog export. how do I retain that signal?
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<ktemkin> Amaranth automatically connects up the default clock and reset for you when *it* creates sync itself. If you create it, you’ll have to get the domain’s clock and reset signals with ClockSignal(“sync”) and ResetSignal(“sync”) and hook them up to your platform’s clock and reset, yourself.
<byteit101> Aha, looks like I don't even have to hook them up to anything when I'm just exporting to verilog
<whitequark> yeah. to add to what ktemkin said, since I think you're using verilog.convert, I suggest using `ports=[domain.clk, domain.rst]` which is really what the platform is doing internally
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<byteit101> hmm, how do I do that? aka what object is domain? top.d.synch.clk isn't a property