<JohnHenry>
I guess I don't know what "no protections" means. Does that mean the RWX bits?
<JohnHenry>
sorear: thank you again, that's very helpful :)
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<heat>
JohnHenry, PROT_NONE is an mmap thing. basically you can set certain pages to not be accessible
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<JohnHenry>
this is gonna get into filesystem stuff isn't it
<heat>
nope
<JohnHenry>
Are there things I need to look out for when _PAGE_PRESENT is 0 but _PAGE_PROT_NONE is 1? Are daemons going to come around and screw around with that page?
<JohnHenry>
But yeah setting a page to be inaccessible (i.e. foiling the hardware page walker) is exactly what I want to do
<heat>
the trick here is that linux uses the page tables to store the backing pages directly. which, if you set to PROT_NONE, you need to do V=0 but still "keep" the page address around, for when munmap comes to reap pages
<heat>
so basically when you set a range to PROT_NONE you'll see !pte_present but pte_protnone
<heat>
and you need _PAGE_PROT_NONE to distinguish PROT_NONE from other types of special page table entries (swap entries, for instance)
<JohnHenry>
that makes sense
<JohnHenry>
so I guess I'm trying to make a new kind of special page table entry that won't collide with the others
<heat>
what are you doing, and why can't that use the existing stuff?
<JohnHenry>
and I'm trying to tell if using _PAGE_PROT_NONE is the right thing to do
<JohnHenry>
I have some TLB manipulation registers
<JohnHenry>
and I want to designate a VMA as an area I'm gonna watch closely
<JohnHenry>
to track the TLB-residence of its PTEs
<JohnHenry>
so I'll madvise to mark the VMA, and it will flush all those PTEs from the TLB and mark them invalid
<JohnHenry>
now accesses to that VMA will fault
<JohnHenry>
I'll use my TLB manipulation registers to soft-load the TLB and mark their presence in my FSM
<heat>
oh, just clear the A bits?
<JohnHenry>
and then if/when shootdown time comes, I have extra data I can use to filter shootdown requirements
<heat>
hmm, riscv has hardware A bits right? maybe that doesn't quite work if you *need* it to fault
<JohnHenry>
It's not clear to me that clearing the A bit is sufficient on the particular machine I have (Milk-V Pioneer with the Sophgo 64-core thing)
<Tenkawa>
JohnHenry: nice
<sorear>
with rva23 you can force A=0 to fault by setting menvcfg.ADUE=0
<JohnHenry>
yeah sadly the SG2042 doesn't follow rva23, it's... like 2019 or so
<JohnHenry>
and my understanding from emailing Thead is that the hardware page walker Just Does Everything
<JohnHenry>
which is why I wanted V=0 so I get faults
<JohnHenry>
Tenkawa: Thank you, this is my master's project so hopefully it works :)
<Tenkawa>
I hope this Spacemit-K1 I'm working with will get more mainline attention sooner than later
<heat>
JohnHenry, cant you just poll the A bits from time to time?
<JohnHenry>
That doesn't tell me which core looked at it though
<JohnHenry>
It's essentially a wager that a given VMA's pages will be looked at by only one or a few harts despite the process running on lots of harts
<JohnHenry>
that's why I'm using madvise to pick the VMA, that's the kind of thing a programmer should know about
<heat>
right, i guess you do need to fault then
<JohnHenry>
but then I have to keep careful track of the TLB residency so that they can't sneak one past me and get a stale TLB entry somewhere
<JohnHenry>
it's the best I've got so far
<JohnHenry>
if this masters project goes well I want the follow-on project to be a hardware extension that makes this kind of work less agonizing
<JohnHenry>
I am learning to appreciate the MIPS software-loaded TLB with this stuff
<JohnHenry>
anyway thank you sorear and heat
<heat>
you're welcome
<heat>
it's possible you can squeeze a bit off of swap ptes or work around it in some way, but you'll need to dig a little deep into linux mm
<heat>
it's probably not exactly a trivial modification, but so it goes ;)
<JohnHenry>
indeed. that's why I'm looking at PROT_NONE and it seems similar to what I want to but it seems like there might be baggage I'm not understanding right away
<JohnHenry>
I wish Lorenzo Stoakes' publisher would hurry up, I need that book so I can understand WTF is going on
<heat>
well the trick is distinguishing real PROT_NONE ptes from your fake "PROT_NONE"
<JohnHenry>
That would be one good way, but it might also just be good to use it as-is, and know that the machine will actually be accessing the PROT_NONE pages as long as it's TLB-resident?
<heat>
i don't understand your question
<heat>
PROT_NONE accesses /will/ page fault, that's its whole shtick
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<JohnHenry>
right
<JohnHenry>
and then I soft-load the massaged-to-set-Valid entry into the TLB
<JohnHenry>
and the user program hums long none the wiser
<JohnHenry>
I just need to make sure the kernel isn't going to see I've marked this otherwise-normal page as PROT_NONE and do something surprising to it
<heat>
i would not do that, unless you have a clear understand that that is your vma
<heat>
so, madvise MADV_JOHNHENRY and then mprotect it PROT_NONE
<JohnHenry>
my plan was to have the user programmer madvise the area they want this to happen to
<JohnHenry>
so they should be pretty sure it's their VMA
<JohnHenry>
ah, belt-and-suspenders
<JohnHenry>
does it break something for me to PROT_NONE it at the madvise step?
<heat>
it'll be very confusing when you start faulting things in and perms come out uneven or somtehing :)
<JohnHenry>
ah now I see the collision between RWX and my special PROT_NONE you were talking about
<JohnHenry>
I don't want to look like that at the user level, so perhaps I should use different bits... will have to look more closely
<JohnHenry>
thanks again
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<heat_>
JohnHenry, i'd advise you to join #mm on oftc (at some other time, its late!)
<heat_>
you might get better help there (we're a little offtopic here too)
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