sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<davidlt_> conchuod, do you have time to provide feedback on: [PATCH v6] clk: starfive: jh7110-sys: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz ?
davidlt_ is now known as davidlt
<conchuod> @davidlt Why do I need to provide feedback on a clk patch?
<davidlt> @conchuod, well, Xingyu asked for your input ~10 days ago.
<conchuod> davidlt: Oh, I didn't notice. I'll try to look later today so.
<davidlt> Thanks!
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