sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<xypron> I guess for Ghostwrite mitigation we want to set VS=0 in mstatus in OpenSBI on C906, C908, C910.
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<courmisch> only C910/C920 are known to be affected by GhostWrite
<courmisch> the HCF bug in C906 is not preventible by OpenSBI at all
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<sorear> VS in mstatus is writable through sstatus, sstatus.VS and mstatus.VS are the same pair of bits and they're already set to 0 at boot
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<sorear> so you're not proposing a change to opensbi
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<clever> sorear: we talked before about XIP needing an mmu, and now actual hw has spawned, where XIP would be extremely valuable, but it lacks an MMU!
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