sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<conchuod> smaeul: Ended up working from home today, I'll get that info tomorrow instead...
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<clemens3> i guess it's no news here
<gurki> they should at least have removed the "the gold standard for riscv computing" part when copypasting the press release ^^
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<dh`> press releases are for releasing to the press, not for editing :-p
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<palmer> smaeul:
<palmer> oop
<palmer> I thought the D1's SBI timer was broken for some reason, and that's why we dropped it from the DT? I can't find the thread, though
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<smaeul> palmer: there was some discussion about the fact that C9xx CLINT doesn't have memory-mapped mtime, so it's not compatible with SiFive CLINT, but the C9xx binding was added since then
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<palmer> smaeul: I remember it being something else, like the timer would stop ticking after a while if we did some SBI twiddling of some sort
<palmer> but maybe that was just some OpenSBI bug?
<smaeul> you're referring to the timer state getting lost in non-retentive suspend?
<palmer> nah, because that one I remember ;)
<palmer> but maybe I just had a ghost memory from mixing up the other two bugs...
<palmer> IIRC it was around when we were talking about changing the priorities of one of the drivers, and we had to make sure they lined up so we didn't use the wrong one
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<smaeul> hmm, I don't remember any bugs around that... and I don't see anything on the ML around that time (2021-2022) that looks like what you
<smaeul> are describing
<palmer> ya, I couldn't find it either. So maybe I'm just crazy ;)
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<ja_02> palmer we all are just a bit crazy LOL
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<palmer> ja_02: ya, I guess sometimes I say "maybe I'm crazy" when I mean "maybe I'm wrong" -- there's no maybe about the crazy ;)
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