sorear changed the topic of #riscv to: RISC-V instruction set architecture | https://riscv.org | Logs: https://libera.irclog.whitequark.org/riscv | Matrix: #riscv:catircservices.org
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<inad922> In case anyone needs a gdb with python support for Risc-V the way to build it is to clone https://github.com/riscv-collab/riscv-gnu-toolchain and then `./configure --prefix=/opt/riscv && GDB_TARGET_FLAGS_EXTRA="--with-python=$(which python)" make` . Obviously replace the prefix and the python path as needed.
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<cousteau> Hi!
<cousteau> In GCC, -O2 results in misaligned branch targets (if the C extension is enabled), despite of -falign-labels being enabled by -O2. Is that normal? This can cause extra delay on certain RISC-V implementations; I understood the point of enabling that option in -O2 was to avoid this delay.
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<cousteau> -falign-labels=4 works fine, but -falign-labels doesn't align the labels at all, so I don't get why that'd be added to -O2.
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<palmer> cousteau: can you file a GCC bug? It sounds like a bug, we probably just missed something
<cousteau> (asking because maybe the default alignment for -falign-labels should be changed, which I suppose is something the RISC-V developers are the ones in charge of fixing)
<cousteau> palmer: OK, but I first wanted to make sure this was indeed a bug
<cousteau> The GCC documentation for -falign-labels says that with no default value it might just be 1 meaning no alignment.
<cousteau> But maybe that's only for architectures where misalignment has no consequences (e.g. VLIW ones like Intel where instructions can typically be as short as one byte)
<palmer> Ya, but if everyone else is aligning them we probably should too. It'll really depend on performance, though, so we'll have to go talk about it
<palmer> So not 100% sure it's a bug, but it's at least worth discussing
<cousteau> Also I'm not sure if misaligned branch targets are an issue on most RISC-V implementations. They are in CVE4
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<cousteau> I did notice an important performance penalty on a very tight loop with/without alignment. (10 clock cycles per iteration with alignment, 11 without, so like a 10% slower)
<palmer> Ya, they're slow on some implemtations. It's pretty common
<palmer> At a bare minimum we should get the tuning defaults right, I don't think we even have one for that uarch? So maybe that's the answer here
<cousteau> I also couldn't manage to figure out where the default value of -falign-labels is changed in the GCC code.
<cousteau> Yeah, there only seem to be -mtune parameters for SiFive stuff.
<cousteau> Anyway I have no idea where those tuning parameters are all defined
<cousteau> So where exactly do I report this? GCC mailing list? Some RISC-V specific one?
<palmer> If you can post that loop, then bugzilla is probably the best bet. Otherwise mailing list is fine, just the standard GCC lists
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<palmer> There's probably a TARGET_ macro hook for it, I'd have to read the docs ;)
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<cousteau> One reason I want to know where this is declared is to confirm that this hasn't been fixed yet
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<palmer> cousteau: the docs have a section for `@defmac LABEL_ALIGN (@var{label})` (there's PDF/HTML, I just reade the source)
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<palmer> looks like we're not doing anything special, but most other ports aren't either. So maybe that default behavior is the right thing, or maybe there's another hook we should be using
<palmer> `struct riscv_tune_param` doesn't have any label alignment fields, though. So there's no uarch-dependent label alignment hooks, which I'd argue is a bug if there's uarch-specific alignment performance quirks
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<cousteau> Hm. -falign-labels=256 makes all labels aligned to 256+8 (hex ends in 08). Wonder why the +8
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<cousteau> That's with -O2. With -O1 it's +10 (0xA).
<jrtc27> post-linking?
<cousteau> Uh, not sure. I used godbolt, with "Compile to binary object".
<jrtc27> no then
<jrtc27> that'll just be a relocatable .o
<jrtc27> so presumably this is R_RISCV_ALIGN not yet having been relaxed
<jrtc27> if -mno-relax "fixes" it that'll verify it
<cousteau> I think you're right
<cousteau> There are lots of R_RISCV_ALIGN/BRANCH things
<cousteau> That thwarts my plans to use godbolt for debugging.
<cousteau> Anyway. Does any expert in this sort of thing think that -falign-labels=0 should default to 4 and not 1 (or 2), so that -O2 aligns the branches?
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<palmer> cousteau: there should be a button in Godbolt to link to an executable and then disassemble, not sure if it works though
<palmer> IMO we should have -falign-labels do something reasonable for the tuning we're targeting. For the generic stuff we'd need to go sort that out, but for the uarch-specific tunings it seems pretty straight-forward to just set it to the alignment targets for the system. Probably best to just discuss it upstream, though, hence he bugzilla ;)
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<cousteau> OK, will submit a bug :)
<palmer> cool
<cousteau> Problem is that there are very few supported uarch
<palmer> not sure what'll happen, but I think at least getting the tunings to match the HW should be straight-forward
<cousteau> Most of them (all?) from SiFive. Maybe this is a job for CORE-V/OpenHW?
<palmer> there's more in the recent releases, it's just a matter of getting someone to care enough to write one
<palmer> they're generally pretty easy, as long as the tuning struct supports what you're trying to do then it's just boilerplate
<palmer> and ya, it's generally best to try and get the HW vendor to do this. It's really their thing ;)
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<cousteau> palmer: thanks! :)
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